使用什么方法来确定二进制加法器的时间执行

嗨，
阅读综合报告（syr文件）。
最后，您会找到时序分析。
这只是一个估计，但对于这样一个简单的设计来说是一个相当不错的估计。
它向您展示了关键路径。
同步一个，输入路径和输出路径。
如果没有寄存器，则同步路径将被省略或由输入到输出的组合关键路径替换。
为了获得最可靠的结果，您可以运行实现并生成用于时序仿真的后标准仿真模型。
然后，您可以详细分析每个路径延迟。
评论：
如果我不得不下注，我会说波纹加法器更快。
;-)
猜猜为什么FPGA中有进位链。
另一方面，CLA逻辑必须构建并与普通LUT连接。
检查时间结果，并告诉我是否正确。
有一个很好的综合 
Eilert



以下为原文

Hi,
read the synthesis report (syr file).
 
At the end you find a timing analysis.
It's just an estimation, but a fairly good one for such a simple design.
 
It shows you the critical paths.
The synchronous one, the input path and the output path.
 
If you have no registers, the synchronous path will either be left out or replaced by the combinatorical critical path from input to output.
 
to obtain the most reliable results, you can run an implementation and generat a post-par simulation model for a timing simulation. Then you can analyze every path-delay there in detail.
 
Comment:
If I had to place a bet, I would say the ripple adder is faster. ;-)
Guess why there are carry chains in the FPGA.
The CLA logic on the other hand has to be build and wired up with normal LUTs.
 
Check the timing results, and tell me if I'm right or not.
 
Have a nice synthesis
  Eilert

感谢您的响应eilert。
我没有注册我的加法器，当我做综合时，我只是有这样的评论：
----对于加法器波纹携带-----------------------------------
最小周期：未找到路径时钟前的最小输入到达时间：未找到路径时钟后的最大输出所需时间：未找到路径最大组合路径延迟：6.626ns
---- for adder look head -------------------------------- 
最小周期：未找到路径时钟前的最小输入到达时间：未找到路径时钟后的最大输出所需时间：未找到路径最大组合路径延迟：6.837ns
--------------------------------------------------
-------------------------------------
因此，使用最大组合路径延迟，我可以确定我的设计速度？
谢谢
Charko



以下为原文

Thank you for your response eilert.
 I have no register for my adders  and when i do synthesis i just have this comment:
---- For adder ripple carry-----------------------------------
 Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 6.626ns
----for adder look head--------------------------------
   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 6.837ns
---------------------------------------------------------------------------------------
So with the maximun combinational path delay, i can determine the speed of my designs?
Thanks
Charko

你好Charco，
那是对的。
正如预期的那样，您的CLA-Adder比纹波加法器慢约0.2 ns。
:-)
检查不同总线宽度的结果，以查看此参数的效果。
我猜你现在测试了一个4位加法器，bot如何改变16,32或64位？
增加是线性的吗？
您也可以尝试将寄存器放在加法器的前面和后面。
并确保在综合中禁用IOB-FF。
因为您现在获得的值包括IBUF和OBUF元素，这些元素与内部逻辑相比非常慢。
通过寄存器之间的加法器，您可以获得仅包含inernal元素的时钟路径。
输出延迟的时钟也可能在该路径中，但这是现实的，因为在大多数情况下，无论如何都必须处理流水线逻辑。
有一个很好的综合 
Eilert



以下为原文

Hi Charco,
 
That's correct. And as expected your CLA-Adder is about 0.2 ns slower than the ripple adder. :-)
Check the results for different buswidths, to see the effect of this parameter.
I guess you tested a 4 bit adder now, bot how do things change with 16, 32 or 64 bit? Is the increase linear?
 
Also you might want to try to put registers in front and behind the adder.
And make sure that using IOB-FFs are disabled in synthesis.
Because the values you got now include the IBUF and OBUF elements which are very slow compared to the internal logic.
With the adder in between registers you get a clocked path which involves only inernal elements. Probably the clock to output delay will be in that path too, but that is realistic, because in most real cases you will have to deal with pipelined logic anyway.
 
Have a nice synthesis
  Eilert

嗨eilert。
我使用的加法器是12位，但是当我测试加法器4位时，我有4.760 ns，当我改变12或16位时它会增加。
所以我应该把注册放在加法器的前面和后面，但我不知道如何在合成中禁用IOB-FF。
另一个问题是我的加法器没有时钟。
我的加法器的输入必须有一个时钟？
非常感谢它非常有帮助。
Charko



以下为原文

Hi eilert.
 
The adder that i used is 12bit but when i test for adder 4 bit i have 4.760 ns and when i change for 12 or 16 bit it is increase.
So i should be put register in front and behind the adder but i don't no how i can disabled IOB-FFs in synthesis.
An other question my adders do not have a clock. The input of my adder must be have an clock?
Thank very much it's very helpfull.
 
Charko

嗨charko，
在ISE 11中，选项名称是
将I / O寄存器打包到IOB中
右键单击合成并选择“过程属性”时，可以更改选项。
该选项位于“Xilinx特定选项”选项卡中。
将其设置为“否”。
您无需更改加法器模块。
只需编写一个带有两个寄存器进程的简单顶层模块，然后在那里实例化你的加法器。
当然，Toplevel模块需要一个时钟。
可以在ISE中的“语言模板”浏览器中找到注册过程的模板。
有一个很好的综合 
Eilert



以下为原文

Hi charko,
in ISE 11 the option name is
Pack I/O Registers into IOBs


You can change the options when you right-click on synthesis and choose "Process Properties".
The option is in the "Xilinx specific Options" Tab. Set it to "No".
 
 
You don't need to change your adder module.
Just write a simple toplevel module with two register processes and instantiate your adder there.
The Toplevel module, of course,  needs a clock.
 
Templates for the register processes can be found in the "Language Templates" Browser within ISE.
 
Have a nice synthesis
  Eilert


 


 
 

嗨！
我承诺我可以把clk放在顶级模块中，但我不能把clk放在加法器中。
我这样做，当我做综合时，我有这样的评论：最小周期：1.552ns（最大频率：644.496MHz）时钟前的最小输入到达时间：2.011ns时钟后的最大输出所需时间：4.181ns最大组合路径延迟：
4.640ns
我使用virtex5，我使用加法器4bit，你可以在附件中看到。
我的合成没有任何警告也没有错误。
现在我可以比较我的设计，为我的应用选择合适的设计。
非常感谢您的帮助。
Charko



以下为原文

Hi eilert!
 
I undertand that i can put clk in top module but i can't put clok in adder. I have do like this and when i do synthesis i have this comment:
   Minimum period: 1.552ns (Maximum Frequency: 644.496MHz)
   Minimum input arrival time before clock: 2.011ns
   Maximum output required time after clock: 4.181ns
   Maximum combinational path delay: 4.640ns
I work with virtex5 and i used adder 4bit as you can see in attachement. I have no warning and no error for my synthesis.
Now i can compare my designs to choose in appropiate design for my application.
 
Thank you very much for your help.
Charko
 

嗨Charko，
我看到你明白了。
电路中只有一个小缺陷。
所有输入和输出都需要注册。
所以，Cin和Cout也应该有FF。
;-)
有一个很好的综合 
Eilert



以下为原文

Hi Charko,
I see you got the idea.
There's just one little flaw in your circuit.
ALL inouts and outputs need to be registered.
So, Cin and Cout should have a FF too. ;-)
 
Have a nice synthesis
  Eilert

嗨艾勒特，
好的，我已经用FF注册了Cin和Cout（你可以看到附件）​​。
所以我现在想要确定偏移量和偏移量以放入约束编辑器中。
我现在如何抵消和抵消ISE！？
我有一个想法来确定偏移量和偏移量。
我认为我应该在综合报告中展示，但我不确定： 
时钟前的最小输入到达时间：1.037ns我认为它是时钟后最大输出所需时间的偏移：3.793ns我认为它偏移了
再次感谢您的回复。
Bahnan



以下为原文

Hi Eilert,
 
Ok  i have registered Cin and Cout with FF( you can see attachement).
So i now i want to determine the offset in and offset out to put in the constraint editor. How i can now offset in and offset out with ISE!?
I have an idea to determine offset in and offset out. think i should be show in synthesis report but i am not sure:
    Minimum input arrival time before clock: 1.037ns    i think it is offset in
    Maximum output required time after clock: 3.793ns i think it offset out


 
Thank you again for your response.
 
Bahnan