VHDL中while循环中的警告

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rourabpaul wrote:
I want to make a modulus program by VHDL code, 
I have made this code 


library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity modulus is 
port (clk : in std_logic; 
x: in std_logic_vector(2 downto 0); 
y: in std_logic_vector(2 downto 0); 
p: out std_logic_vector(5 downto 0)); 
end modulous; 
architecture modulus_arch of modulus is 
signal n : std_logic_vector(2 downto 0); 
signal s1: std_logic_vector(5 downto 0); 


begin 
main: process(x,y,n,clk) 
begin 
if(rising_edge(clk)) then 
while s1<=x loop 
n<=n+"001"; 
s1<=n*y; 
end loop; 
p<=x-y*(n-"001"); 
n1<=n; 
end if; 
end process main; 
end modulus_arch; 


there is no error indeed, 
compilation,simulation, synthesize , implementation have been done , 

but when i want to see in test bench wave form following warning has been seen 


//WARNING:Simulator:29 - at 10.000 ns(1): Warning: There is an 'U'|'X'|'W'|'Z'|'-'// 

and dont show the desired output 

here i gave "110" in 'x'.& "011" in y, 
i want to calculate 5 mod 3, 
so output should be 2, 
but i found '6hXX'

答案对人有帮助，有参考价值 0

rourabpaul wrote:

"

Wow, that's some awful code. The sensitivity list is wrong. And you really need to understand the whole notion of non-blocking signal assignments. Signals DO NOT update in the manner that you clearly expect.
 

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PLEASE do NOT send me a PM asking for help with your project/homework."

it may be my project or home work,but im expecting a solution from this site,but when u are telling about a problem
then its also necessary to indicate the problem,whats the problem in my code ?if you dnt, then you also should not poke your nose in this topic,

 
 
 
First -- I'll poke my nose where I wish.
Second -- you should not expect a solution.
Third -- the problem is your code.
 
 
 
 

im have also tried this program removing 'clk' from sensitivity list,and also initialized 's1' as "000001" and 'n' as "000"  ,but the problem is same,
u can also try this code in your simulator,
 

 
A) clk is the only signal that should be on the sensitivity list!
B) the signal n1 is never declared anywhere, so the code doesn't even compile.
C) You should NOT use std_logic_arith, use numeric_std instead.