大型多路复用器怎么实现

您的术语“case-when”，“with-select”，“if-then”或“when-else”是HDL行为方式来描述多路复用器和“AND-OR结构”：是标准门级实现的
复用器。
合成器将选择最佳门级实现（在当前的Xilinx架构中，LUT和MUXF＃组合的组合将LUT实现为用于HDL功能的AND-OR方程。
>我还想知道如何在VHDL实体中声明所有输入信号
这没有任何意义，除非你没有VHDL经验。如果你没有VHDL经验，那么我建议你选一本好的VHDL书并开始阅读。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Your terms "case-when", "with-select", "if-then" or "when-else" are HDL behavioral ways to describe a multiplexer and an "AND-OR structure": is a standard gate level implementation of a multiplexer.
 
The synthesizer will select an optimal gate level implementation (which in current Xilinx architectures will be a combination of LUTs and MUXF# combinations with the LUTs implemented as AND-OR equation  for your HDL functionality.
 
> I would also like to know how to declare all the input signals in a VHDL entity
 
This doesn't make any sense, unless you have no VHDL experience..  If you have no VHDL experience then I would suggest that you pick up a good VHDL book and start reading.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

在我的上一个问题中，我问是否可以在实体中声明一个std_logic_vector数组。
因为否则我被迫宣布100个不同的std_logic_vector输入。



以下为原文

In my last question I ask if is it possible to declare an array of std_logic_vector in the entity. Because otherwise I am forced to declare 100 different std_logic_vector inputs.

您的参考资料或Google对std_logic_vector数组的说法是什么？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

And what does your reference material or Google say about std_logic_vector arrays?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

fpgasparatodos写道：
在我的上一个问题中，我问是否可以在实体中声明一个std_logic_vector数组。
因为否则我被迫宣布100个不同的std_logic_vector输入。
您是否遵循Ed McGett的建议并购买并研究了良好的VHDL参考文本？
----------------------------是的，我这样做是为了谋生。



以下为原文

 

fpgasparatodos wrote:
In my last question I ask if is it possible to declare an array of std_logic_vector in the entity. Because otherwise I am forced to declare 100 different std_logic_vector inputs.

Did you follow Ed McGett's advice and purchase and study a good VHDL reference text?
 
----------------------------Yes, I do this for a living.

我一直在阅读我的问题，我认为它可以通过使用定义std_logic_vector类型数组的包来解决。
如果您知道其他解决方案，我将非常感谢您的建议。



以下为原文

I have been reading about my problem, and I think that it may be solved by using a package that defines the array of std_logic_vector type. If you know other solution I will appreciate the suggestion.

fpgasparatodos写道：
我一直在阅读我的问题，我认为它可以通过使用定义std_logic_vector类型数组的包来解决。
如果您知道其他解决方案，我将非常感谢您的建议。
嗯，该包名为std_logic_1164，与定义std_logic的包相同。
现在，去买一本Peter Ashenden的“VHDL设计师指南”。
在你读完这本书之前不要继续。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

fpgasparatodos wrote:
I have been reading about my problem, and I think that it may be solved by using a package that defines the array of std_logic_vector type. If you know other solution I will appreciate the suggestion.

 
Uhhh, that package is called std_logic_1164, and is the same package that defines std_logic.
 
RIGHT NOW, go buy a copy of Peter Ashenden's "The Designer's Guide To VHDL." Do not continue until you've read the book.
----------------------------Yes, I do this for a living.

我想你可以礼貌地回复。
此外，如果您知道解决方案并且它非常简单，则只需30秒即可完成。
我发现人们使用他们自己的包（我不会谈论std_logic_1164）来定义std_logic_vector类型的数组，然后用这种新的数据类型声明输入/输出端口：
http://objectmix.com/vhdl/396975-array-entity-declaration.html
http://www.velocityreviews.com/forums/t601398-passing-arrays-via-port-map.html



以下为原文

I think that you can reply more politely. Moreover if you know the solution and it is so easy, it takes only 30 seconds to write it. 
 
I have found that people use their own package (and I don't talk about std_logic_1164) to define the array of std_logic_vector type and then declare the input/output ports with this new data type:
 
http://objectmix.com/vhdl/396975-array-entity-declaration.html
http://www.velocityreviews.com/forums/t601398-passing-arrays-via-port-map.html
 
 

我认为你无法判断巴斯曼及其回应。
这是一个FPGA设计支持论坛（不是HDL语言教学课程论坛），您要问的是VHDL最基本的知识可以回答的问题。
你来到这个论坛寻求帮助和建议，你给出的建议是（部分）学习你用于设计的语言。
你应该考虑接受这个建议，而不是因为没有人在银盘上把你的设计交给你。
这个论坛的人们普遍理解，如果你不理解语言基础知识，你很可能会遇到一系列无休止的障碍。
这些同样的人试图向您传达，学习语言将帮助您理解和解决您的原始问题......并使您成为更好的设计师，更好地适应自己。
您可以接受建议与否，这取决于您。
就个人而言，我对那些没有尽力帮助自己并在此过程中学习的人失去耐心。
我不为Xilinx工作，所以不要将我的意见用于代表Xilinx的客户支持方法。
我不是要吝啬或侮辱，但（我认为）你会得到报酬，成为一名设计工程师，学习工具是你工作的一部分。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I don't think you have any standing to judge Bassman and his response.  This is an FPGA design support forum (not a HDL language teaching course forum), and you are asking questions which the most basic knowledge of VHDL would answer.
 
You came to this forum asking for help and advice, and the advice you were given was (in part) learn the language you're using for design.  You should consider accepting that advice rather than acting wounded because no-one handed your design to you on a silver platter.
 
The folks in this forum generally understand that if you don't understand the language basics, you are likely to have a never-ending series of roadblocks with which to contend.  These same folks are trying to convey to you that learning the language will help you understand and solve your original questions...  and make you a better designer, better equipped to fend for yourself.
 
You can take the advice or not, it's up to you.  Personally, I lose patience with folks who don't make an honest effort to help themselves and learn in the process.  I don't work for Xilinx, so don't take my comments to represent Xilinx' approach to customer support.  I'm not trying to be mean or insulting, but (I presume) you get paid to be a design engineer, and learning the tools is part of your job.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

fpgasparatodos写道：
我想你可以礼貌地回复。
此外，如果您知道解决方案并且它非常简单，则只需30秒即可完成。
我发现人们使用他们自己的包（我不会谈论std_logic_1164）来定义std_logic_vector类型的数组，然后用这种新的数据类型声明输入/输出端口：
http://objectmix.com/vhdl/396975-array-entity-declaration.html
http://www.velocityreviews.com/forums/t601398-passing-arrays-via-port-map.html
这些包正在讨论数组的数组，或者更准确地说，是std_logic_vectors的数组。
他们仍然需要std_logic_1164来声明std_logic和std_logic_vector类型。
所以我确实给了你简单，正确的答案。
如果你不喜欢这个答案，那就是你的问题。
不过，谢谢你的演奏。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

fpgasparatodos wrote:
I think that you can reply more politely. Moreover if you know the solution and it is so easy, it takes only 30 seconds to write it. 
 
I have found that people use their own package (and I don't talk about std_logic_1164) to define the array of std_logic_vector type and then declare the input/output ports with this new data type:
 
http://objectmix.com/vhdl/396975-array-entity-declaration.html
http://www.velocityreviews.com/forums/t601398-passing-arrays-via-port-map.html
 
 

 
Those packages are talking about arrays of arrays, or more correctly, arrays of std_logic_vectors. They still need std_logic_1164 to declare both the std_logic and std_logic_vector types.
 
So I did give you the easy, and correct, answer. If you don't like the answer, that's your problem.
 
Thanks for playing, though.
----------------------------Yes, I do this for a living.