32个比较器可以提供32比1多路复用器吗？

阅读XST用户指南，它包括为MUX，FSM，锁存器，寄存器等功能编写“样式”。
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- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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以下为原文

Read the XST user guide, it includes coding "styles" for functions such as MUXes, FSMs, latches, registers, etc.
 
You can access the XST user guide from the ISE Navigator HELP menu.
 
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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你需要优先考虑吗？
如果是这样，那么您的选择是有限的。
但是如果你能够容忍管道中的延迟，可以考虑创建一个由32个注册比较器组成的存储库，每个比较器对应一个pxX。
比较优先级编码器中的32个寄存器所需的逻辑比测试所有比较器要少得多。
----------------------------是的，我这样做是为了谋生。



以下为原文

Do you need the priority? If so, then your options are limited. But if you can tolerate the latency in a pipeline, consider creating a bank of 32 registered comparators, one for each of pxX. Comparing 32 registers in a priority encoder takes a lot less logic than testing all of the comparators.
----------------------------Yes, I do this for a living.

pxX信号是当前x，y栅格位置的像素颜色索引。
每个pxX颜色来自“精灵”移位寄存器，精灵可以与最低精灵数最高的“分层”重叠。
因此，如果sprite0（px0）不是0，它的像素颜色将显示，如果它是0，那么如果它不是0，则可以显示下一个sprite的像素。因此，我认为我需要描述的电路涉及prioirty。
使用移位寄存器是我正在复制的原始电路如何工作，但它在水平线上只有4个可能的精灵，并且使用FPGA我可以完成所有32个。但是，解析精灵在给定的x，y处显示
我正在使用的VHDL正在导致约束问题。
我可以想到使用单个移位寄存器（并行工作）的唯一其他选择是使用行缓冲器并将像素信息从最高精灵覆盖到最低。
但是，我不确定这会更有效率吗？
我想这将是一个寄存器文件，如：
signal pixel_buf：整数范围0到15的数组（0到384）;
所以这样我就会在检索像素数据时解析像素选择，并在水平线的时间内对其进行传播。
但我也必须加倍缓冲，所以我可以填充一个缓冲区，同时显示另一个缓冲区。
马修



以下为原文

The pxX signals are pixel color indexes for the current x,y raster location.  Each pxX color is from a "sprite" shift register, and sprites can overlap with the "layering" going from lowest sprite number being the top-most.  So if sprite0 (px0) is other than 0, its pixel color will show, if it is 0, then next sprite's pixel may be shown if it is not 0, etc.  Thus, I think the circuit I need to describe involves prioirty.
 
Using shift registers is how the original circuit that I'm reproducing worked, but it only had 4 possible sprites on a horizontal line, and with the FPGA I can do all 32.  However, resolving the sprite to display at a given x,y with the VHDL I'm currently using is causing the constraint problem.
 
The only other alternative I can think of to using individual shift registers (which work in parallel), would be to use a line buffer and overlay the pixel information from highest sprite to lowest.  However, I'm not sure this would be any more efficient?  I guess it would be a register file, something like:
 
signal pixel_buf : is array (0 to 384) of integer range 0 to 15;
 
So this way I would be resolving the pixel selection as the pixel data is retrieved, which spreads it over the time of a horizontal line.  But I would have to double buffer too, so I could populate one buffer while displaying the other.
 
Matthew