[问答]

在System Generator设计运行时修改参数的常用方法是什么？

问答对人有帮助，内容完整，我也想知道答案 0 大家好，我正在使用具有Virtex-4 FX100的定制板。在内部，有一个基于VHDL的框架，它将定制板上的不同部分与“DSP内核”连接，后者是在System Generator下开发的。在这个System Generator设计中，我想在FPGA运行时改变一些变量。例如，希望能够从“外部世界”修改特定ASR的长度，或控制多路复用器以手动选择不同的信道。在设计运行时修改这些参数的常用方法是什么？因为我想在ChipScope上思考这个DSP核心后输出一些数据，它是否可以用来修改设计参数？我已经阅读了有关硬件协同仿真的内容，但我不知道这是否真的是我想要的，因为SysGen设计不是整个设计的顶级设计。此外，此设计的频率为312 MHz，这可能会影响所选解决方案以修改参数。问候，乔治以上来自于谷歌翻译以下为原文 Hi all, I am working with a custom board which has a Virtex-4 FX100. Inside, there is a VHDL-based framework which interfaces the different parts on the custom board with the "DSP core", which is developed under System Generator. In this System Generator design, there are some variables that I would like to change while the FPGA is running. For instance, it would be desirable being able to modify the length of a particular ASR, or control a multiplexer to select different channels manually, from the "outside world". Which is the common approach to modify those parameters while the design is running? As I will have to output some data after this DSP core I was thinking on ChipScope, can it be used to modify the parameters on the design as well?. I have read about Hardware co-simulation, but I don't know if that is really what I am looking for, as the SysGen design is not the top level in the whole design. Also, the frequency of this design is 312 MHz, which may have an influence on the chosen solution to modify the parameters. Regards, Jorge 0
2019-1-15 10:39:11　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答举报李丽虹相关推荐 • Labview运行时菜单的颜色修改 8137 • labview RT的前面板在自动运行时是怎么处理的 4904 • Touchgfx在运行时如何更改整个屏幕？ 264 • 请问单选按钮的布尔文本可以在运行时通过程序修改吗？ 4453 • labview中是否能使控件在运行时变灰，在不运行时正常。 3538 • 电机在不运行时有很大的电流声是什么原因造成的？ 1098 • 请问运行时模型是什么？ 832 • labview运行时修改控件属性问题 4479 • 如何将采集到的两组数据实时显示在xy图中,并且在labview每次运行时都清除所采集得到的数据? 9389 • System Generator中的PID控制器是如何设计的？ 1628 2个回答

答案对人有帮助，有参考价值 0 你有什么样的外部接口？如果您正在寻找想法，串口是最简单的。我不认为chipcope是你正在寻找的。您可以在sysgen中实现地址和数据总线，并使用简单的消息协议将其连接到串行端口。您还可以在HDL结构中实现地址和数据总线，并通过从核心带出的专用信号进行连接。在修改核心参数时，您需要/期望什么样的响应时间？以上来自于谷歌翻译以下为原文 What kind of external interface do you have? A serial port is about the simplest you can get if you are looking for ideas. I dont think chipscope is what you are looking for. You can implement an address and data bus within sysgen and interface it to a serial port with a simple message protocol. You can also implement the address and data bus within the HDL fabric and connect it via dedicated signals that are brought out of the core. What kind of response time do you need/expect when you are modifying the parameters of the core?

2019-1-15 10:49:40 评论举报张润

答案对人有帮助，有参考价值 0 我有一个串行端口和一个JTAG连接器。串口库在VHDL框架上，但我认为可以修改它以便与sysgen核心接口。您是否知道在使用嵌入在更大系统中的sysgen核心时是否可以使用硬件协同仿真？响应时间并不重要。我只需要改变它，不要介意它是否需要几秒钟。感谢您的投入，我期待的东西比简单的串口更困难，我没想到:) 以上来自于谷歌翻译以下为原文 I have both a serial port and a JTAG connector. The serial port library is on the VHDL framework, but I think it could be modified in order to interface with the sysgen core. Do you know if using hardware co-simulation is possible when using the sysgen core embedded on a bigger system? The response time is not critical. I just need it to change, don't mind if it takes even a couple of seconds. Thanks for the input, I was expecting something more difficult than just a simple serial port, I didn't think about that :)

2019-1-15 11:09:21 评论举报李慧