怎么在vhdl中实现三角形过滤器结构

嗨，
所以最重要的是，你提供的绘图具有开始设计所需的一切。
累加器级0..2的四个寄存器需要时钟使能，来自SCU（Load_ST0..2）。
您必须编写三个计数器，能够对应ROM并且比较和多路复用器是单行的。
加法器也很简单。
只有需要更多考虑的事情才是乘数。
是否允许延迟？
你是否影响了来自SCU的负载信号的时序？
增益计数器是如何控制的？
整个数据路径可以在单个时钟进程中编写（可能没有乘法器）。
然后树的进程为计数器和一些进程或ROM的实例，你就完成了。 
有一个很好的综合 
Eilert



以下为原文

Hi,so what's the big deal, the drawing you provided has everything you need to start your design.The four registers of Accumulator Stage 0..2 need clock enables, that come from the SCU (Load_ST0..2).You have to write three counters, capable of adressing the ROMs and the Compare and Mux are one-liners. The adder is simple too. Only thing that needs more consideration is the multiplier.Is there latency allowed? Do you have influence to the timing of the Load signals coming from the SCU?How is the Gain counter controlled?  The whole Datapath can be written in a single clocked process (maybe without the multiplier).Then tree processes for the counters and some processes or instances for the ROMs, and you are done. Have a nice synthesis  Eilert