verilog代码编译错误

嗨，
我正在尝试为我的一个assignmnet编写一个简单的cpu电路的verilog代码。
我尝试过几个程序，但在尝试使用设计时遇到了编译错误。
我把它简化为一个基本的cpu，它有一个带有ALU的控制器和一个内存块。
在此阶段，ALU只能添加/减去无符号数。
我想使用xilinx库中的RAM16x4作为内存并在我的程序中实现它。
如果有人可以帮我弄清楚代码中的错误，我写的代码如下。
我很可能能够在原理图模块中单独使用控制器和RAM并通过相关端口连接它们，但我很想知道代码中的错误。
非常狡猾。
module cpu（reset_cpu，clock，run）;
输入时钟，reset_cpu，run; //输出[3：0] mar，mbr_inout; //输出mem_write; reg [3：0] pc，ir，mar，mbr，dreg; reg fetch_complete，mem_write; wire clock，reset_cpu，
跑;
RAM16X4S mem1（.O0（mbr_inout（0））,. O1（mbr_inout（1））,. O2（mbr_inout（2））,. O3（mbr_inout（3））,. A0（mar（0））,. A1
（mar（1）），。A2（mar（2）），。A3（mar（3））,. D0（mbr_inout（0）），。D1（mbr_inout（1）），。D2（mbr_inout（2）
），。DW3（mbr_inout（3））,. WCLK（时钟）,. WE（mem_write））;
总是@（posedge clock）beginif（reset_cpu）pc = 0; fetch_complete = 0; else case（fetch_complete）1'b1：beginir [1：0] = mbr [3：2]; mar [1：0] = mbr [
1：0]; case（ir）4'bxx00：开始mem_write = 0;
mbr = mbr_inout;
dreg = mbr;
结束// load4'bxx01：开始mem_write = 0;
mbr = mbr_inout;
dreg = dreg + mbr;
结束// add4'bxx10：开始mem_write = 0;
mbr = mbr_inout;
dreg = dreg  -  mbr;
结束// subtract4'bxx11：开始mbr = dreg;
mbr_inout = mbr;
mem_write = 1;
;
结束// storeendcaseend1'b0：开始// wt = 0;
mem_write = 0; mar = pc; mbr = mbr_inout; pc = pc + 1; fetch_complete = 1; endendcase endendmodule



以下为原文

Hi,

I am trying to write a verilog code for a simple cpu circuit for one of my assignmnets. I have tried few programs but got compiling errors when trying to inplement the design. I have simplified it to a basic cpu which has controller with a ALU in it and a memory block. At this stage ALU can only add/subtract unsigned numbers. I want to use the  RAM16x4s from xilinx library as the memory and instatiate it in my program. The code I have written is below if someone can help me to figure out the mistake in the code. I most probably will be able to use the controller and RAM seperately in a schematic module and connect them through the relevant ports, but I am keen to figure out the error in the code.

Thnaks very much.

module cpu(reset_cpu, clock, run);
input clock, reset_cpu, run;
//output [3:0] mar, mbr_inout;
//output mem_write;
reg [3:0] pc, ir, mar, mbr, dreg;
reg fetch_complete, mem_write;
wire clock, reset_cpu, run;
RAM16X4S mem1 (.O0 (mbr_inout(0)), .O1 (mbr_inout(1)), .O2 (mbr_inout(2)),.O3 (mbr_inout(3)),
       .A0 (mar(0)),.A1 (mar(1)), .A2 (mar(2)), .A3 (mar(3)),
       .D0 (mbr_inout(0)), .D1 (mbr_inout(1)), .D2 (mbr_inout(2)), .D3 (mbr_inout(3)),
       .WCLK (clock), .WE (mem_write));
always @(posedge clock)
begin
if (reset_cpu)
pc=0;
fetch_complete =0;
else
case (fetch_complete)
1'b1 :
begin
ir[1:0] = mbr[3:2];
mar[1:0] = mbr[1:0];
case (ir)
4'bxx00 : begin mem_write =0; mbr = mbr_inout; dreg = mbr;  end // load
4'bxx01 : begin mem_write =0; mbr = mbr_inout; dreg = dreg + mbr; end // add
4'bxx10 : begin mem_write =0; mbr = mbr_inout; dreg = dreg - mbr ; end // subtract
4'bxx11 : begin mbr= dreg; mbr_inout = mbr; mem_write =1; ; end// store
endcase
end
1'b0 :
    begin
//wt =0;
mem_write=0;
mar = pc;
mbr= mbr_inout;
pc=pc+1;
fetch_complete =1;
end
endcase
end
endmodule