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我有一个电路,它被分成两个独立的半部分,但是在一个面板上一起生产。
首先分别通过IPG细分两个板,然后将两个CAD合并为一个面板; 到现在为止还挺好。 但是......为了节省生产过程,这两块电路板现在已经通过连接两块电路板的几根互连带状电缆到达ICT。 (当从支撑品中分开时,两块板然后简单地折叠在一起)。 我不能保证两组CAD之间没有重复的节点名称。 我尝试将两者合并为一块板(即不再嵌入并包括电缆连接),但关于节点名称的最后一点使得这非常危险。 我看不到将一块板的互连结合到另一块板的简单方法。 您不能作为面板在IPG中作为面板进入IPG中的节点库,因为每种板类型仅呈现其自己的内部节点(即,布线的一侧)以供选择。 将两个CAD合并为一个的尝试也失去了我的板旋转(一个270转,另一个90)和偏移。 我敢肯定必须有办法克服这个问题,但我似乎总是不断碰到砖墙,无论我试图解决这个问题。 目前还没有建立固定装置,但我想将两块板和互连结合起来,以便更好地进行IPG分析和夹具布线。 我必须将这项工作作为一个单独的对运行,并且仅在构建夹具后尝试为布线开发节点lib测试吗? 我担心这会导致分析不良并且保护许多初始测试。 有没有其他人遇到这种情况并找出克服它的最佳方法? 在此先感谢DML 以上来自于谷歌翻译 以下为原文 I have a circuit which has been split into two separate halves but are produced together on the one panel. Ran both boards up through IPG fine separately at first and then the two CADs were amalgamated into a single panel; so far, so good. BUT... In order to save a production process these two boards are now to arrive at ICT with a couple of interconnecting ribbon cables already linking the two boards. (When split from the supporting fret the two boards then simply fold together). I cannot guarantee that there is no duplication of node names between the two sets of CAD. I tried merging the two into one board (i.e. no longer panelised and including the cable connections) but the last point about node names makes that very dangerous. I cannot see an easy way of incorporating the interconnections from one board across to the other. You cannot enter a Node Library in IPG across the board pair as a panel as each board type only presents its own internal nodes (i.e. one side of the cabling) for selection. The attempt to merge the two CAD into one also lost my board rotations (270 for one, 90 for the other) and offsets. I'm sure there must be a way to overcome this but I just seem to keep coming up against a brick wall whichever way I try to approach the problem. No fixturing has yet been built but I would like to incorporate the two boards AND the interconnections for better IPG analysis and fixture wiring. Must I run up the job as a separate pair and only try to develop a node lib test for the cabling after the jig is built? I fear this will result in poor analysis and guarding for many initial tests. Has anyone else come across this scenario and worked out the best way to overcome it? Thanks in advance, DML |
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多年前我这样做了,我不记得细节了。
但最近我分析了一个电路板的节点,我记得这个细节。 首先,您需要分析电路板没有相同的节点名称。 可能GND是重复的,所以我建议手动将GND节点名称更改为其中一个baord(或任何其他名称)的GND_,因为它确定两者之间会有一个跳线并且你想要测试 在GND和GND之间有一个跳线。要分析节点名称,我建议使用vi编辑电路板,只获取节点列表。 可能还有其他方法可以做到这一点,但我发现这很容易和半自动。 * + Bold Italics是vi命令+ * 1.将板保存为节点格式1.1用vi打开板文件的副本。 2.搜索CONNECTIONS + * / CONNECTIONS * + 3.将光标定位在CONNECTION行并删除+ *:1上方的所有内容。 del * + 4.使用以下vi宏删除设备的连接* +:map F jmb / ; ^ Md'b + * 4.1为了在vi宏行中插入^ M使用* Ctrl-V然后* 4.2这是什么vi 宏做的是映射* F *键(你可以使用任何其他字母)首先向下移动一行并将其标记为b(开头,但你可以用任何其他字母命名)然后搜索*; *( 因为它是一个需要用转义反斜杠写的特殊字符,然后按Enter键,然后从那里删除到* b *标记.5。你所要做的就是将光标放在节点文件的开头并点击 * F *多次删除所有设备和引脚,你的文件将只有你的节点列表.6。删除文件上的所有空格+ *:1,$ s / // g * + 6.1这样做 对于两个板文件.7。您可以创建一个ksh脚本来验证没有重复节点,但是使用以下Unix命令* + cat node1 node2>节点创建一个包含两个节点列表的新文件更容易 .csv + * 8.你可能会 t在执行粘贴命令之前在node2文件上添加标记,以便识别文件的开头。 我推荐一个假节点名称,如:BOARD2NODES 9.在MS Excell上打开文件nodes.csv并使用自动格式化功能突出显示重复项。 此方法仅用于验证是否没有重复的节点。 可能使用sed更自动,但我仍然想看看我在做什么。 您需要手动更改Board Consultant上的名称。 我推荐Board Consultant,因为它会改变board和board_xy上的名字。 希望没有比GND更多的重复。 我在我的项目中做了什么(如果我不记得它错了)是我手动创建跨越电路板边界的跳线测试,例如:连接到1:GND连接s到2:GND_跳线8 ....但是 我瘦了有更好的方法来做到这一点。 要创建单个板,我认为最好的方法是使用CAD转换器来做到这一点。 TestSight能够处理i3070板文件作为输入,因此我认为可以轻松地合并两者(并让TestSight容纳坐标,偏移和旋转)以在最后创建单个板和board_xy。 然后,创建PDL(部件描述语言)以创建跳线非常简单。 然后IPG将能够考虑两个板上的所有周围电路。 一旦你的电路板合并,绘制你的灯具,以验证所有测试点落在正确的x,y位置希望这会有所帮助。 以上来自于谷歌翻译 以下为原文 I did this many years ago and I don't recall the details. But recently I analyze a board's nodes and I recall this with details. First you'll need to analyze that the board's does not have the same node names. Probably GND is the one that is repeated, so I recommend to manually change the GND node name to GND_ on one of the baord (or any other name) since it is sure that there will be a jumper between the two and you want to test that there is a jumper between GND and GND_ To analyze the node names I recommend using vi to edit the board and only get the list of nodes. There might be other ways to do it, but I found this easy and semi-automatic. *+Bold Italics are vi commands+* 1. Save the board as Node Format 1.1 open a copy of your board file with vi. 2. Search for CONNECTIONS +*/CONNECTIONS*+ 3. Position your cursor at the CONNECTION row and delete everything above +*:1,. del*+ 4. Delete Device's Connections using the following vi macro *+:map F jmb/;^Md'b+* 4.1 In order to Insert ^M in the vi macro line use *Ctrl-V then * 4.2 What this vi macro do is to map the *F* key (you can use any other letter) to first move one row down and mark that as b (for beginning, but you can name it with any other letter) then search for *;* (since it is a special character needs to be written with the escape backslash, then hit enter, then delete from there to the *b* mark. 5. All you have to do is position your cursor at the beginning of your node file and hit *F* as many times to delete all devices's and pins and your file will end have a list of only your nodes. 6. Delete all spaces on the file +*:1,$ s/ //g*+ 6.1 Do this for both board files. 7. You can create a ksh script to verify that there are no repeating nodes, but it is easier to just create a new file with the two list of nodes with the following Unix command *+cat node1 node2 > nodes.csv+* 8. You might want to add a marker on the node2 file at the very beginning before doing the paste command in order to identify the beginning of the file. I recommend a fake node name like: BOARD2NODES 9. Open the file nodes.csv on MS Excell and use the Auto Formatting function to highlight duplicates. This method is just to verify if there are no repeated nodes. Probably using sed is more automatic, but I still like to view what I'm doing. You'll need to manually change the names on Board Consultant. I recommend Board Consultant since it will change the names on both board and board_xy. Hopefully there are no more duplicates than GND. What I did on my project (if I don't recall it wrong) was that I manually create tests for the jumper wires crossing board boundaries like: connect a to 1:GND connect s to 2:GND_ jumper 8.... But I thin there are better ways to do it. To create both boards as single I think the best method is to use your CAD converter to do that. TestSight is able to handle i3070 board files as inputs so I think is possible to easily merge both (and let TestSight accommodate coordinates, offsets and rotations) to create a single board and board_xy at the end. It is then simple to create a PDL (Part Description Language) to create your jumpers. Then IPG will be able to consider all surrounding circuitry on both boards. Once you have your boards merged, plot your fixture to verify all testpoints lands on the right x,y location Hope this helps. |
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嗨,我会选择1个板,并重命名板和board_xy中的al节点,即“Sign123”变为“2_Sign123”。 您的带状电缆会造成短路,但没关系,那么您就知道有连接。 重命名后,将2个板和board_xy“粘合”在一起。 绘制一个新的轮廓,你有一个新的“胶水”板(没有面板)。 也许你必须转移board_xy以使它们定位良好。 我会附上一个脚本来移动xy coords。 用法:(将脚本放在c: Agilent_ict scripts中并运行c:/ Agilent_ict / scripts / shift_xy board_xy x-shift y-shift> shifted_xy祝你好运 以上来自于谷歌翻译 以下为原文 Hi, I would pick 1 of the boards, and rename al nodes in board and board_xy, i.e. "Sign123" becomes "2_Sign123". Your ribbon cables will cause a short, but thats ok, then you know connection is there. After rename, "glue" the 2 board and board_xy together. Draw a new outline and you have one new "glue-ed" board (no panel). Maybe you have to shift board_xy to get them positioned well. I'll attached a script to shift xy coords. usage:(put script in c:Agilent_ictscripts and run where c:/Agilent_ict/scripts/shift_xy board_xy x-shift y-shift > shifted_xy Good luck 附件
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非常感谢所有回复的人。 最后,它是最简单的单独一对,然后在功能区连接测试中手动添加。 在两个CAD中更改节点名称前缀以确保不会混淆。 在最后期限到来之前,不能花太多时间试图变得聪明! 所有发布和工作正常。 感谢你们的支持! DML。 以上来自于谷歌翻译 以下为原文 Many thanks to all who replied. In the end did it the simplest way as a separate pair and then manually added in the ribbon connection tests. Altered node name prefixes in both CADs to ensure no confusion. Can't spend too much time trying to be clever when the deadlines are coming! All released and working fine. Thanks for the support, guys! DML. |
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