基于TPS561201的4.5V至17V输入、1A同步降压SWIFT转换器

2018-11-16 16:56:28 1347 转换器瞬态

0 　　1 特性　　TPS561201 和 TPS561208 1A 转换器集成了 140mΩ 和 84mΩ FET 　　D-CAP2™模式控制，用于快速瞬态响应　　输入电压范围：4.5V 至 17V 　　输出电压范围：0.76V 至 7V 　　脉冲跳跃模式 (TPS561201) 或持续电流模式 (TPS561208) 　　580kHz 开关频率　　低关断电流(小于 10µA) 　　2% 反馈电压精度 (25°C) 　　从预偏置输出电压中启动　　逐周期过流限制　　断续模式过流保护　　非锁存欠压保护 (UVP) 和热关断 (TSD) 保护　　固定软启动时间：1.0ms 　　使用 TPS56120x 并借助 WEBENCH® Power Designer 创建定制设计方案　　2 应用　　数字电视电源　　高清蓝光™光盘播放器　　网络家庭终端设备　　数字机顶盒 (STB) 　　安全监控　　3 说明　　TPS561201 和 TPS561208 是采用 SOT-23 封装的简单易用型 1A 同步降压转换器。　　此器件被优化为使用尽可能少的外部组件即可运行，并且可以实现低待机电流。　　这些开关模式电源 (SMPS) 器件采用 D-CAP2 模式控制，从而提供快速瞬态响应，并且在无需外部补偿组件的情况下支持诸如高分子聚合物等低等效串联电阻 (ESR) 输出电容器以及超低 ESR 陶瓷电容器。 TPS561201 可在脉冲跳跃模式下运行，从而能在轻载运行期间保持高效率。TPS561201 和 TPS561208 可提供 6 引脚 1.6 × 2.9 (mm) SOT (DDC) 封装，额定结温范围为 –40°C 至 125°C。该产品品牌下其它产品相关信息可咨询拍明芯城官网　　The TPS561201 and TPS561208 are 1-A synchronous step-down converters. The proprietary D-CAP2 mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2 mode control can reduce the output capacitance required to meet a specific level of performance. 　　The main control loop of the TPS561201 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. 　　At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 mode control. 　　The TPS561201 and TPS561208 have an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator. If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converters ramp up smoothly into regulation point. 　　The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. 　　During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. 　　There are some important considerations for this type of over-current protection. The load current is higher than the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time (typically 24 µs) and restart after the hiccup time (typically 15 ms). 　　When the over current condition is removed, the output voltage returns to the regulated value. 0
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