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大家好，我正在研究一个简单的电路与PIC12LF1501应该被激活的开关，保持自己的动力通过一个PMOS + NMOS对（PMOS器件绕过电源开关，NMOS驱动PMOS），并关闭自己关闭NIC晶体管通过PIC的RA5，这是主动驱动低。现在的问题是，当电源以这种方式关闭，端口RA5切换到H输出，一旦电源电压下降到约1伏-这就足以再次切换电源。这种情况总是发生，不管我如何配置RA5。我可能需要通过分频网络来驱动NMOS，将栅极电压降低到低于VTH @ 1伏特电源电压，但我想知道是否还有另一种解决方案（如果其他人遇到了同样的问题）。NMOS器件具有相当宽的VTH范围，在0.6到1.5伏特之间，这是复杂的，这只会带来3伏电源电压的问题。也许我最好在这里切换到一个NPN双极晶体管…谢谢你对这件事的任何想法！
以上来自于百度翻译 以下为原文 Hi all, I'm working on a simple circuit with a PIC12LF1501 that is supposed to be activated with a switch, keeping itself powered up via a PMOS+NMOS pair (the PMOS device bypassing the supply switch, NMOS to drive the PMOS), and switch itself off by turning off the NMOS transistor through the PIC's RA5, which is actively driven low. The problem now is that when the power is switched off in this manner, port RA5 switches to a H output as soon as the supply voltage drops to approximately 1 volt -- and this is enough to switch the power back on again. This always happens, regardless how I configure RA5. I probably need to drive the NMOS via a divider network to lower the gate voltage to below Vth @ 1 volt supply voltage, but I wondered if there is another solution to this (and if other people experienced the same problem). It is also complicating that the NMOS device has a rather wide Vth range, between 0.6 and 1.5 volts -- which presents a bit of a problem with only 3 volts supply voltage. Perhaps I'd better switch to an NPN bipolar transistor here ... Thanks in advance for any thoughts on this matter! 
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11个回答
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在N-MOS门上有什么值下拉？对于类似的用途，我通常使用100-200 K.此外，I二极管或开关和PIC输出。
以上来自于百度翻译 以下为原文 What value pulldown do you have on the N-MOS gate? For similar uses I generally use 100-200k. Also, I diode-or the switch and the PIC output. |
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目前，没有下拉电阻，而是一个1UF的上限，有一个100K系列电阻从RA5，但这显然没有办法。我会用下拉电阻做一些测试，但是这当然有增加“ON”状态下的电源电流的缺点（我现在正处于一个桃色10UA，100K下拉这会增加四倍）。我也不能再增加NMOS门上的RC时间（现在0.1s），因为这样我就有一个问题，即开关必须持续一段时间，以确保它保持不变。但是谢谢你的快速回复！
以上来自于百度翻译 以下为原文 At the moment, there's no pull-down resistor but instead a 1uF cap, with a 100K series resistor from RA5, but that obviously doesn't do the trick. I'll do some testing with pull-down resistors, but that of course has the drawback of increasing the supply current drawn in the 'on' state (I'm at a peachy 10uA right now, and with 100K pull-down this would increase fourfold). I also can't increase the RC time (now 0.1s) on the NMOS gate any further, because then I'd have the problem that the switch must be pressed for that duration to make sure it stays on. But thanks for the quick reply! |
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HIE直接下拉是必须的，因为PIC引脚会在电源关闭时恢复到高阻抗（输入），留下NMOS门浮动。可能你所看到的是BOR的全部或部分的结果。
以上来自于百度翻译 以下为原文 Hi The direct pull-down is a must because the PIC pins will revert to high impedance (inputs) when powering off, leaving the NMOS gate floating. Probably what you are seeing is the result of a total or partial BOR. Best regards Jorge |
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嗨，豪尔赫，这里的谜题是为什么NMOS栅极被拉高甚至电容器接地，它似乎是保护二极管的正电源电压：这是肖特基型，它具有不可忽略的漏电流。我把一个普通的硅二极管，加上一个1m的下拉电阻好的测量，现在一切都很好，只有一个小的增加on on the电流。嗯，快乐的微动力设计微笑：谢谢你的思考，最好的问候，
以上来自于百度翻译 以下为原文 Hi Jorge, The puzzler here was why the NMOS gate was pulled high even with a capacitor to ground, and it appears that it was the protection diode to the positive supply voltage: that was a Schottky type, which has a non-negligible leakage current. I put in a normal silicon diode, plus a 1M pull-down resistor for good measure, and now things are fine, with only a small increase in on-state current. Ah well, the joys of micropower design Smile: Thanks for thinking along, Best regards, |
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NMOS门的1UF上限是什么原因？NMOS的开关性能将受到不利影响。
以上来自于百度翻译 以下为原文 What is your reason for the 1uf cap on NMOS gate? NMOS switching performance would be adversely affected by this. |
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使用电容器代替下拉电阻器的原因是使ON状态下的电流消耗最小化，因为整个事情由一个小的锂硬币电池供电，并且每个微安计计数。当RA5被拉低时，帽被放电，并且在0.1秒之后，PMOS器件被切换。F，电源电压开始下降。这个想法是，当RA5在1V电源电压下进入高阻抗关断模式时，这个帽应该保持NMOS门处于一个限定的低电平。不幸的是，当RA5被完全关断时，保护二极管开始再次拖动栅极电压。因为从电源电容器汲取的总电流接近零，所以有足够的时间将栅极电容再次充电到高于VTH。因此，我放弃了这个“聪明”的想法，接受了一个小的额外的电流消耗；当然，我再次认识到肖特基二极管不是阿尔瓦。YES作为保护二极管的最佳选择，特别是在处理非常小的电流时。
以上来自于百度翻译 以下为原文 The reason for using a capacitor instead of a pull-down resistor was to minimize current drain in the on-state, as the whole thing is powered by a small lithium coin cell, and every microamp counts. When RA5 is pulled low, the cap is discharged, and after ~0.1 seconds, the PMOS device is switched off, and the secnodary supply voltage starts to drop. The idea was that this cap should keep the NMOS gate at a defined low level when RA5 would go into high-impedance off-mode at ~1V supply voltage. Unfortunately, a protection diode started dragging the gate voltage up again as soon as RA5 was fully switched off. And because total current draw from the supply capacitor approached zero, there was enough time to charge the gate capacitor again to above Vth. So I just abandoned this whole 'smart' idea, and accept a small extra current drain; and of course I learned (once again) that Schottky diodes are not always the best choice as a protection diode, in particular when dealing with very small currents. |
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电容器是该项工作的错误选择，因为采用浮动引脚，电容器有可能拿起电荷并添加到NMOS门上的任何电荷，而NMOS门只是另一个电容器。理想的电容器没有电荷流过它，它只是储存电荷。最好的选择是1M电阻器来泄放晶体管栅极上的任何电荷并保持关闭。你不需要一个保护二极管，除非你希望在引脚上静电或反向电压，然后齐纳二极管或转炉将更好地工作，以限制电压瞬变。在这种情况下，我认为不会有任何帮助。如果你只是想确保你的NMOS保持关闭，你可以把电阻值稍微提高到2.2M，这只会画出理论上的1.5 UA@ 3V3。这同样适用于PMOS。你需要确保有一个电阻器来泄放任何累积电荷，显然它应该去V+来保持晶体管关闭。这将需要一些实验来找出功率和可靠性之间的最佳平衡。
以上来自于百度翻译 以下为原文 A capacitor was the wrong choice of component for that job because with a floating pin it is possible for the capacitor to pick up charge and add to any charge on the NMOS gate which is just another capacitor. An ideal capacitor has no charge flowing through it, it just stores charge. The best choice was the 1M resistor to bleed off any charge accumulating on the transistor gate and keep it turned off. You shouldn't need a protection diode unless you are expecting electrostatic or reverse voltages on the pin and then a zener diode or transorb would do a better job to limit voltage transients. Which in this case I don't think would be any help. If you are just trying to make sure your NMOS stays off you could up the resistor value slightly to 2.2M which will only draw a theoretical 1.5uA @3V3. The same applies to the PMOS. You need to make sure there is a resistor to bleed off any accumulated charge there and obviously it should go to V+ to keep that transistor off. It will take some experimentation to find the best balance between power and reliability. |
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我想他指的是内置PIC I/O引脚的保护二极管。
以上来自于百度翻译 以下为原文 I think he's referring to the protection diode built in to the PIC I/O pin. |
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当电压高于VDD+0.3V或低于GND-0.3V时，这些二极管只能通过电流。如果Vdd通过切断电源完全切断电路，我不知道会产生什么影响。应该没有电流去哪里。我怀疑一些其他引脚可能有一些连接到VDD或静电电荷积累。不确定会问海报为感兴趣的示意图。谢谢你指出了这一点。
以上来自于百度翻译 以下为原文 Those diodes should only pass current when the voltage is above Vdd +0.3V or below GND - 0.3V. I am not sure what the effect is if Vdd is disconnected from the circuit by cutting the power supply altogether. There should be no where for the current to go. I suspect some of the other pins may have had some connection to Vdd or electrostatic charge build up. Not sure will have to ask poster for a schematic out of interest. Thanks for pointing that out @qhb. |
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我知道，下拉电阻是最好的选择，以确保NMOS栅极保持在0伏。电容器的想法是将栅极保持在足够长的电压以使电源电压下降到（接近）零，但回想起来，它比优点有更多的缺点。NMOS门上的保护二极管是一个额外的预防措施，因为在那里有很高的直流阻抗。停电模式，以避免可能产生的静态电荷（整个设备是便携式的，静电很容易发生当它被携带在某些类型的织物中）。无论如何，我把设计修改成一个更传统的方法，现在一切都好了，只有一个当前消费适度增长——也感谢您的投入：
以上来自于百度翻译 以下为原文 I know that a pull-down resistor is the best choice to ensure that the NMOS gate stays at 0 volts. The idea of the capacitor was to keep the gate at that voltage for long enough to allow the supply voltage to drop to (near) zero, but in retrospect, that had more drawbacks than advantages. The protection diode on the NMOS gate was an extra precaution because of the very high DC impedance there in power-down mode, to avoid possible buildup of static charge (the whole device is intended to be portable, and static electricity can easily happen when it is carried around in certain types of fabric). Anyway, I modified the design to a more traditional approach, and all is fine now, with only a very modest increase in current consumption -- also thanks to your input :) |
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欢迎您，并感谢您的后续信息。全面理解思维过程总是好的。祝你的项目好运。听起来很有趣。
以上来自于百度翻译 以下为原文 You are welcome and thanks for that follow up information. It's always good to fully understand the thought processes. Good luck with your project. It sounds interesting. |
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