Vivado结果不一致

我正在使用Vivado 2018.1在spartan 7（xc7s50csga324-1）中实现一个设计。
我有一个有效的设计，并计划逐步添加功能。
但是，正如我所做的那样，我偶尔会得到在硬件中没有按预期工作的构建。
起初，我认为这只是错误。
当我深入研究它时，这个问题似乎与逻辑无关 - 我通过稍微修改逻辑，删除逻辑和/或添加逻辑来进行实验 - 有时候构建会在考虑到变化的情况下按预期工作，有时它不起作用。
举个例子：我修改了设计，将寄存器A绑定到一个常量 - 设计工作。
当一个简单的控制信号被断言（即寄存器写入发生）时，我修改了设计以更新寄存器A  - 设计没有按预期工作。
我修改了设计，根据更复杂的控制信号断言更新寄存器A（即在一系列事件之后设置控制） - 设计工作。
对于没有按预期工作的构建，破坏的构建似乎表现出相同的方式。
似乎与设计没有任何关联。
我尝试了多次迭代插入调试探针（除了sims也没有显示任何问题），没有任何运气找到问题。
但是，我尝试了一个奇怪的结果的实验​​是当我将调试探针添加到工作版本时。
没有探针，构建工作。
使用探针，构建不起作用。
我也尝试过增量版本，但这似乎也没有任何区别。
所有构建都已通过计时（即使使用调试探针）。
该设计具有一个时钟域（100MHz）。
所有io路径（除了一些不关心）都受到限制。
LUT利用率仅为5％左右，但是使用率超过70％。
没有意外的syn或par警告。
brams上有一些drc错误（1839/1840错误用于brams上的异步/同步复位）但是，据我所知，这些并不是意料之外的（即使ram控制信号同步复位，我也无法摆脱它们）
。
是否有任何关于导致这些不一致结果的建议？



以下为原文

I am implementing a design in a spartan 7 (xc7s50csga324-1) using Vivado 2018.1.  I have a design that worked and was planning on gradually adding functionality.  However, as I did this, I was occasionally getting builds that did not work as expected in hardware.  At first, I thought it was just bugs.  As I dug into it, the problem does not seem to be related to logic - I experimented by slightly modifying the logic, removing logic, and/or adding logic - sometimes the build worked as expected considering the changes and sometimes it did not work.   As an example: I modified design to tie register A to a constant - the design worked.  I modified design to update register A when a simple control signal asserted (i.e. register write occurred) - the design did not work as expected.  I modified design to update register A based on a more complicated control signal assert (i.e. control is set after a series of events) - the design worked.

For the builds that did not work as expected, the broken builds all seemed to behave the same way.  There does not seem to be any correlation to the design.  I tried numerous iterations of inserting debug probes (besides sims which also did not show any issue) without any luck finding the issue.  However, one experiment I tried with odd results was when I added debug probes to a working build.  Without the probes, the build worked.  With the probes, the build did not work.  I also tried doing incremental builds but that did not seem to make any difference either.

All builds have passed timing (even with the debug probes).  The design has one clock domain (100MHz).  All io paths (except for some don't cares) are constrained.  LUT utilization is only around 5%, but bram utilization is over 70%.  There are no unexpected syn or par warnings.  There are some drc errors on the brams (1839/1840 errors for async/sync resets on brams) but, as I understand it, these are not unexpected (nor can I get rid of them even though the ram control signals are reset synchronously).

Are there any suggestions on what can be causing these inconsistent results?