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我正在为这个PIC32 MZ2048 EFG064移植一个特定的TCP/IP协议栈。现在,我正在尝试通过描述描述符的功能,通过尝试传输一个描述符链,并在逻辑分析仪上从TXEN、TXD0和TXD1引脚中看到活动。这看起来应该很简单,但我遇到了一个问题,我已经没有任何想法可以尝试了。在附加的代码中,我有三个以太网TX描述符,并且每个都有一个缓冲区。如果我用MESET将每个缓冲器的内容设置为任意的值(0x14),则我的逻辑分析器显示第一帧包含数据,但是第二和第三在每个帧的开始和结束时不只是一个或两个。EthFrMTxOK=3,这是我所期望的。但是,如果我不初始化缓冲区,MAC不会传输任何东西。MAC引脚没有活动,EthFrMTxOK保持在零。如果我在每个缓冲区填充一个合成的SA、DA和长度,它仍然不传输。我已经阅读了以太网数据表6000,1155D,我找不到任何解释。它似乎是足够简单的,它应该简单地传输缓冲区中的内容,但有些东西挂起。如果我改变0xC400 0180值,所以缓冲区长度不同,例如to0xc2000 180,该帧是其他长度的一半,所以我知道这是有效的。我使用了和声EX。足够让事情更接近。以前基本上没有任何事情发生,现在有一些东西从RMII接口出来,并不是预期的。有人在PIC32 MZ上使用了MAC吗?我相信它与PIC32 MX上的相同,但是MX移植到MZ的例子甚至不起作用。我现在想要的是成功传输以太网帧,并在每一帧上看到数据。
以上来自于百度翻译 以下为原文 I'm working on porting a specific TCP/IP stack to this PIC32MZ2048EFG064. Right now I'm experimenting with it by learning how the descriptors function by trying to transmit a chain of descriptors and watch for activity out of the TXEN, TXD0, and TXD1 pins on a logic analyzer. This seems like it should be simple enough but I'm running into a problem I no longer have any ideas to try. In the attached code I have three ethernet Tx descriptors, and each has a buffer. If I set the contents of each buffer to some arbitrary value (0x14) with memset, my logic analyzer shows the first frame contains data, but the 2nd and 3rd do not other than a bit or two at the start and end of each frame. ETHFRMTXOK = 3, which is what I'd expect. However if I don't initialize the buffers, the MAC won't transmit anything. There's no activity out of the MAC pins, and ETHFRMTXOK remains at zero. If I populate a made-up SA, DA, and length in each buffer, it still doesn't transmit. I've read through the Ethernet datasheet 60001155D, and I can't find anything to explain this. It seems straightforward enough that it should simply transmit what's in the buffer, but something is hanging up. If I change the 0xc4000180 value so the buffer length is different, for example to 0xc2000180, that frame is half the length of the others so I know that's working. I have used a HARMony example to get things closer. Previously essentially nothing was happening, now something is coming out of the RMII interface, just not what's expected. Has anyone used the MAC on the PIC32MZ? I believe it's the same as what's on the PIC32MX, but examples for MX ported to MZ don't even work. All I want right now is to successfully transmit ethernet frames and see data on each one. Attachment(s) main.c (7.62 KB) - downloaded 34 times |
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查看代码:MeSET(&;(TxBuff[0)],0x14,PIC32 MZYEXTXXBuffelyStand);…TxBuffelDeSc(0)。地址=(UTI32 32 t)KVAY-TYPA((;(TXBuff[0)]),并且同样记住该处理器具有高速缓存。这个MeMSET将更新缓存中的数据,但可能不会在物理内存中更新。因此,当您启动传输时:EthCON1SETIONEYCON1YTXRTSH掩码;谁知道ETH控制器在这些描述符中看到什么。可能没有什么有意义的。确保要么将所有数据刷新到内存,要么使用未经访问的访问。
以上来自于百度翻译 以下为原文 Looking at your code: memset(&(txBuffer[0][0]), 0x14, PIC32MZ_ETH_TX_BUFFER_SIZE); ... txBufferDesc[0].address = (uint32_t) KVA_TO_PA(&(txBuffer[0][0])); and similar Keep in mind that this processor has a cache. This memset will update the data in the cache, but probably not in the physical memory. So, when you initiate the transmit: ETHCON1SET = _ETHCON1_TXRTS_MASK; who knows what the ETH controllers sees in those descriptors. Probably nothing that makes much sense. Make sure that either you flush all the data to memory or use uncached accesses. |
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我认为我在PRECON没有改变任何比特,但显然缓存仍然在做什么?在任何情况下,我都尝试了AySyc();我不知道该怎么想。当然,我应该在TXD0和TXD1上进行很多活动,而不是在开始和Endo.EdEd中进行一些转换:我读了一些关于缓存的内容,发现DMA内存区域应该使用相干属性将其放入未被清除的KSGE1中。有趣。我得试试这个。这可以解释为什么最初的MX芯片的端口代码不工作,尽管以太网外设基本上是相同的。
以上来自于百度翻译 以下为原文 I thought I had that all disabled by not changing any bits in PRECON, but apparently the cache is still doing something? In any case I tried a _sync(); right before ETHCON1SET = _ETHCON1_TXRTS_MASK; and the result is the same. I'm not sure what to think anymore. Surely I should expect a lot of activity on TXD0 and TXD1 when transmitting a frame instead of a few transitions at the start and end. EDIT: I read some more about the cache and found that DMA memory regions should use the coherent attribute to place it into KSEG1 which is uncached. Interesting. I'll have to try this. This may explain why ported code originally for MX chips doesn't work despite the ethernet peripheral being essentially identical. |
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你是对的!要是我几个星期前就知道了就好了。我希望以太网特定的PIC数据表在某个地方提到这一点。这里的例子甚至没有说明这一点,但我认为它最初是为MX编写的。对于以后可能会读到的任何人来说,所有用于DMA的RAM都必须使用“相干”属性,否则你会把头发拔出来的!
以上来自于百度翻译 以下为原文 You were correct! If only I had known this weeks ago. I wish the Ethernet specific PIC datasheet mentioned this somewhere. The examples there don't even account for this, but I think it was originally written for MX. For anyone who might read this later, all RAM used for DMA must use the 'coherent' attribute or you'll pull your hair out! |
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