TMR1中断似乎过早触发

嗨，我试着用PIC18F24K22的比较模块来实现速度测量。为了扩展测量范围，我考虑了time1的溢出，并将它们添加到测量结果中（见周期变量的计算）：这种方法大部分时间工作良好，但是每分钟都发生CCPR2大于CCPR2i最后一次（Time1溢出不能HAV）。E发生）但Time1中断已触发（T1-溢出流计数为1）。在下一次测量中，缺少了Time1中断。看起来Time1中断太早了。下面我附上了一些调试输出示例：原因是什么？亲切的问候，沃尔夫冈



      以下为原文

    Hi,

I’m trying to implement speed measurement with the compare-module of a PIC 18F24K22. To extend the measurement range I’m taking into account the overflows of Timer1 and add them to the measurement result (see calcualtion of period variable):

   
//Initialization:
    //Timer1 config - CCP2 capture
    TMR1CS1 = 0; //Internal clock (Fosc/4)
    TMR1CS0 = 0;
    T1CKPS1 = 1; //11 = 1:8 Prescale value
    T1CKPS0 = 1;
    TMR1GE = 0; //Timer1 counts regardless of Timer1 gate function
    TMR1ON = 1; //Enable Timer1

    //CCP2 config - engine speed measurement
    CCP2M3 = 0; //0100 = Capture mode: every falling edge
    CCP2M2 = 1;
    CCP2M1 = 0;
    CCP2M0 = 0;
    C2TSEL1 = 0; //00 = CCP1 - Capture modes use Timer1
    C2TSEL0 = 0;

    //interrupts
    IPEN = 0; //Disable priority levels on interrupts
    TMR1IE = 1; //Enables the TMR1 overflow interrupt
    CCP2IE = 1; //Enable CCP2 interrupt
    PEIE = 1; //Enables all unmasked peripheral interrupts
    GIE = 1; //Enables all unmasked interrupts

//ISR:
void interrupt myisr(void) {
    static unsigned int t1_overflow_count = 0;

    if (TMR1IE && TMR1IF) { //TMR1 overflow interrupt
        t1_overflow_count ++;        
        TMR1IF = 0; //reset interrupt
    }
    if (CCP2IE && CCP2IF) { //CCP2 interrupt - rev counter
        unsigned int ccpr2 = 0;
        static unsigned int ccpr2_last = 0;
        unsigned long period = 0;

#ifdef DEBUG
        debug_t1_overflow_count = t1_overflow_count;
#endif
        
        ccpr2 = ((unsigned int) CCPR2H << 8) | CCPR2L;      //read capture value
        if(ccpr2 < ccpr2_last)    //if new value is smaller then old value
            t1_overflow_count--;                            //ignore (first) overflow
        
        period = (unsigned long)t1_overflow_count * 0xFFFF + (unsigned int)(ccpr2 - ccpr2_last);

#ifdef DEBUG
        debug_period = period;
        debug_ccpr2h = CCPR2H;
        debug_ccpr2l = CCPR2L;
        debug_ccpr2 = ccpr2;
        debug_ccpr2_last = ccpr2_last;
#endif
        ccpr2_last = ccpr2;
        
        calculate_and_set_x(period); //calculate engine speed and update process variable
            
        t1_overflow_count = 0;
        
        CCP2IF = 0; //reset interrupt
    }


This approach works good most of the time, but every few minutes it happens that ccpr2 is bigger than ccpr2_last (Timer1 overflow can not have happened) but Timer1 interrupt has triggered (t1_overflow_count is 1). At the next measurment the Timer1 interrupt is missing. It looks like the Timer1 interrupt is triggerd too early.
Below I have attached some debug output examples:


ccpr2_last  ccpr2   overlow_count  period
30716        56360  0                    25644         --> correct example
---------------------------------------------------------------------------------------------------------------
32359        65383  1                    98559         --> Timer1 overflow too early
65383        30716  0                    4294867094 --> missing Timer1 overflow
---------------------------------------------------------------------------------------------------------------
32296        65533  1                    98772         --> Timer1 overflow too early
65533        30078  0                    4294866306 --> missing Timer1 overflow
---------------------------------------------------------------------------------------------------------------
33159        65535  1                    97911         --> Timer1 overflow too early
65535        30165  0                    4294866391 --> missing Timer1 overflow


What could be the reason?

Kind regards, Wolfgang