If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter overflow.
用此方法需要考虑到RCR只有8位,以及PWM的edge-aligned and center-aligned模式:
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the
repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until
the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
– the number of PWM periods in edge-aligned mode
– the number of half PWM period in center-aligned mode.
Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
• To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=000).
• Then the Timer2's slave mode controller should be configured in external clock mode 1
(write SMS=111 in the TIM2_SMCR register). This causes Timer 2 to be clocked by the
rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1
counter overflow).
• Finally both timers must be enabled by setting their respective CEN bits within their
respective TIMx_CR1 registers. Make sure to enable Timer2 before enabling Timer1.