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嗨,大家好
我正在尝试设计专用时间段的计数器。 现在我有一个但没有工作我的期望,这就是为什么我在这里:) 该设计的目的是计算~4 us宽3.3v幅度脉冲。 在附件中,您可以看到当前的设计。 我想要做的是在这个专用期间(例如1毫秒)它必须计数,并且在期间结束时指示器(标志)将告诉计数器“Ok立即发送值”。 我观察到的是它没有处理标志并在每个时钟周期后发送计数。 我在设计中使用了两个clks。 一个是125MHz ZYBO原装clk。 其他250KHz clk。 缓慢clk的目的是防止多次计数,因为脉冲远远超过125MHz clk周期。 p.s你知道计数器实现的准确性吗? 我的意思是即使我使用IP计数器,计数的错误是什么? 任何建议都非常欢迎...... 提前致谢 Pulse_Counter.vhd 3 KB 以上来自于谷歌翻译 以下为原文 Hi guys I'm trying to design a counter for a dedicated time period. Now I have one but not working how I expect and that is the reason why I'm here :) The purpose of the design is counting a ~4 us width 3.3v amplitude pulses. In the attachment you can see the current design. What I want to do is during this dedicated period (e.g 1 milisecond) it must count and in the end of the period an indicator (flag) will tell the counter "Ok send the value now". What I observe is it is not taking care of the flag and sending the count after each clock cycle. I've used two clks in the design. One is 125MHz ZYBO original clk. The other 250KHz clk. The purpose of the slow clk is to prevent multiple counts sınce the pulse wıdth ıs far much b'gger then the 125MHz clk period. p.s Do you know the accuracy of the counter implementations. I mean what is the error of counting even if I use the IP counter? Any advice is very welcome ... Thanks in advance Pulse_Counter.vhd 3 KB |
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7个回答
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好。
假设你想要4 us,你有一个125 MHz的时钟(8 ns周期)。 那么你将需要4 us / 8 ns = 500个时钟周期。 所以,我们将判断:常数C_FOUR_MICROSECONDS:整数:= 500; 现在我们需要我们的计数器:signal counter4u:整数范围0到C_FOUR_MICROSECONDS-1:= 0; 然后,您将有一个进程,在计数器启用的每个时钟周期递增计数器(如果它将永久启用,忽略启用行或永久设置为'1': P_INCREMENT_COUNTER:进程(时钟)是 开始 如果rising_edge(时钟)那么 if(enable ='1')然后 counter4u 其他 counter4u 万一; 万一; 结束过程P_INCREMENT_COUNTER; 然后你可以有一个单独的过程来检测计数周期的结束(你可以把它放在同一个过程中,如果你想 - 我喜欢将它们分开。 P_COUNTER_DETECT:进程(时钟)是 开始 如果rising_edge(时钟)那么 if(counter4u = C_FOUR_MICROSECONDS-1)然后 count_end 其他 count_end 万一; 万一; 结束过程P_COUNTER_DETECT; 您可以以几乎完全相同的方式构建边缘检测计数器。 ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 OK. Let's say you want to count for 4 us and you have a 125 MHz clock (8 ns period). Then you will need 4 us/ 8 ns = 500 clock cycles. So, we'll decare: constant C_FOUR_MICROSECONDS : integer := 500; Now we need our counter: signal counter4u : integer range 0 to C_FOUR_MICROSECONDS-1 := 0; Then you will have a process that increments the counter for every clock cycle it is enabled (if it will be permanently enabled, ignore the enable line or set it permanently to '1': P_INCREMENT_COUNTER : process(clock) is begin if rising_edge(clock) then if (enable = '1') then counter4u <= (counter4u + 1) mod C_FOUR_MICROSECONDS; else counter4u <= 0; end if; end if; end process P_INCREMENT_COUNTER; Then you can have a separate process to detect the end of the counting period (you could put it in the same process if you wanted - I like to keep them separate. P_COUNTER_DETECT : process(clock) is begin if rising_edge(clock) then if (counter4u = C_FOUR_MICROSECONDS-1) then count_end <= '1'; else count_end <= '0'; end if; end if; end process P_COUNTER_DETECT; You can build you edge detect counter in almost exactly the same way. ---------- "That which we must learn to do, we learn by doing." - AristotleView solution in original post |
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1.不要使用计数器来生成时钟。
只是不要。 2.不要使用ieee.std_logic_unsigned。 只需使用numeric_std 3.使用原始125 MHz作为系统时钟没有错。 4.将脉冲输入与系统时钟同步(如果它与系统时钟异步)。 5.检查同步脉冲输入的边沿以增加脉冲计数器。 *请勿使用rising_edge(信号)来执行此操作!* 同步设计! ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 1. Don't use counters to generate clocks. Just don't. 2. Don't use ieee.std_logic_unsigned. Just use numeric_std 3. Nothing wrong with using your original 125 MHz as the system clock. 4. Synchronise your pulse input to your system clock (if it is asynchronous to your system clock). 5. Check for edges of your synchronised pulse input to increase your pulse counter. *Do not use if rising_edge(signal) to do this!* Synchronous design! ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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你好@ hgleamon1
withie.std_logic_unsigned有什么问题。 当我删除它时,由于计数器中的总和,我得到了错误。 我看到了一些与脉冲计数有关的方法叫做edge_detector。 可能这会完成我的工作。 提前致谢。 以上来自于谷歌翻译 以下为原文 Hi @hgleamon1 What is the problem with ieee.std_logic_unsigned. when I remove it I got erros because of summattion in the counters. I saw some other methods related to pulse counting called edge_detector. Probably this will do my job. Thanks in advance. |
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尽管它的名字,ieee.std_logic_unsigned不是标准的。
它是一个旧的Synopsys库,完全由实际标准ieee.numeric_std替换(在功能上)。 您可能会因为尝试向std_logic_vector添加值而得到错误,例如 “0001”+ 1,这是不可能的。 最好对计数器使用整数,首先是因为它更容易阅读,其次因为它完全受到numeric_std包的支持。 如果您需要非常大的数字,那么您应该使用与numeric_std完全兼容的有符号或无符号类型。 ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 Despite its name, ieee.std_logic_unsigned is not standard. It is an old Synopsys library that is entirely replaced (in function) by the actual standard ieee.numeric_std. You probably get errors because you try to add a value to a std_logic_vector, e.g. "0001" + 1, which is not possible. It is better to use integers for counters, firstly because it is easier to read and secondly because it is entirely supported by the numeric_std package. If you need very large numbers then you should use signed or unsigned types that are also fully compatible with numeric_std. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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当我改变计数器声明
信号计数器:STD_LOGIC_VECTOR - >信号计数器:INTEGER 我又得到了错误。 我在谷歌上查了一个例子,但我找到的是使用std_logic_vector。 你能给出一个链接或一个例子吗? 谢谢 以上来自于谷歌翻译 以下为原文 When I change the counter declaration signal counter : STD_LOGIC_VECTOR -> signal counter : INTEGER I got error again. I checked for an example on the google but the ones I found were using std_logic_vector. Could you give a link or an example? Thanks |
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好。
假设你想要4 us,你有一个125 MHz的时钟(8 ns周期)。 那么你将需要4 us / 8 ns = 500个时钟周期。 所以,我们将判断:常数C_FOUR_MICROSECONDS:整数:= 500; 现在我们需要我们的计数器:signal counter4u:整数范围0到C_FOUR_MICROSECONDS-1:= 0; 然后,您将有一个进程,在计数器启用的每个时钟周期递增计数器(如果它将永久启用,忽略启用行或永久设置为'1': P_INCREMENT_COUNTER:进程(时钟)是 开始 如果rising_edge(时钟)那么 if(enable ='1')然后 counter4u 其他 counter4u 万一; 万一; 结束过程P_INCREMENT_COUNTER; 然后你可以有一个单独的过程来检测计数周期的结束(你可以把它放在同一个过程中,如果你想 - 我喜欢将它们分开。 P_COUNTER_DETECT:进程(时钟)是 开始 如果rising_edge(时钟)那么 if(counter4u = C_FOUR_MICROSECONDS-1)然后 count_end 其他 count_end 万一; 万一; 结束过程P_COUNTER_DETECT; 您可以以几乎完全相同的方式构建边缘检测计数器。 ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 OK. Let's say you want to count for 4 us and you have a 125 MHz clock (8 ns period). Then you will need 4 us/ 8 ns = 500 clock cycles. So, we'll decare: constant C_FOUR_MICROSECONDS : integer := 500; Now we need our counter: signal counter4u : integer range 0 to C_FOUR_MICROSECONDS-1 := 0; Then you will have a process that increments the counter for every clock cycle it is enabled (if it will be permanently enabled, ignore the enable line or set it permanently to '1': P_INCREMENT_COUNTER : process(clock) is begin if rising_edge(clock) then if (enable = '1') then counter4u <= (counter4u + 1) mod C_FOUR_MICROSECONDS; else counter4u <= 0; end if; end if; end process P_INCREMENT_COUNTER; Then you can have a separate process to detect the end of the counting period (you could put it in the same process if you wanted - I like to keep them separate. P_COUNTER_DETECT : process(clock) is begin if rising_edge(clock) then if (counter4u = C_FOUR_MICROSECONDS-1) then count_end <= '1'; else count_end <= '0'; end if; end if; end process P_COUNTER_DETECT; You can build you edge detect counter in almost exactly the same way. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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你好@ hgleamon1
非常感谢您的贡献。 我搞定了:) 现在尝试进一步改进并行源/计数器...... 以上来自于谷歌翻译 以下为原文 Hi @hgleamon1 Thank you very much for the contribution. I got it working :) Now trying to improve it further for parallel sources/counters... |
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