PWM概念8位微控制器为什么只有CCPR1L寄存器需要设置占空比

1—7.1节说明硬件总是需要IT-2—10位。如果你只需要8B DC分辨率3，你可以把下两个比特（在CCPR1CON）中留下0个-不清楚你在看什么。图11-3很清楚，在CPR1CON中，您将10B DC值的上8b写入CCPR1L和下2B到2B。CCPR1H是只读锁存器以同步DC变化到周期



      以下为原文

    1 - section 7.1 explains it
2 - 10 bits are always needed by the hardware. You can leave the lower two bits (in ccpr1con) as 0 if you only need 8b DC resolution
3 - not clear what you are looking at. Fig 11-3 is pretty clear to me that you write the upper 8b of the 10b DC value to ccpr1l and lower 2b to the 2b in ccpr1con. Ccpr1h is read only latch to sync DC changes to the period

因为它从0到PR，这是PR2 + 1状态。例如，如果PR2＝1，它将计数为0, 1, 0，1, 0, 1…这是每个循环的两个计数。不，CCPR1L保持上8位，而不是更低。“CCP1CON/LT；5:4& GT”被附加到它以获得较低的2位。它不是。你误读了一些东西。这个公式。它说，CCPR1L在循环开始时被复制到CCPR1H，从CPR1L：CCP1CON/LT；5:4和GT的两个比特被复制到附加到CPR1H的两个隐藏位。实际比较是用CCPRH和这两个比特来完成的。这是让你在一个周期中更新CCPRL1，并影响下一个周期。回去阅读并清楚地阅读文本。你误读了注册名，并做出了错误的假设。



      以下为原文

   
Because it counts from 0 to PR, which is PR2+1 states.
e.g., if PR2=1, it will count 0, 1, 0, 1, 0, 1 ...
That is two counts per cycle.
 

No, CCPR1L holds the upper 8 bits, not the lower.
"CCP1CON<5:4>" are appended to it to get the lower 2 bits.
 

It doesn't. You are misreading something.
 

This formula is correct.
 

Yes
 

No it doesn't.
It says that CCPR1L is copied to CCPR1H at the start of a cycle, and the two bits from  CCPR1L:CCP1CON<5:4> are copied to an extra two hidden bits attached to CCPR1H.
The actual comparison is done using CCPRH and those two bits. That is what allows you to update CCPRL1 in the middle of a cycle, and it takes affect on the next cycle.
 

Go back and read the text clearly. You are misreading register names and making bad assumptions from that.
 

好的，谢谢。我还有一个问题：如果占空比是：占空比＝CCPR1L:CPCON & lt；5，4和gt；/（4（PR2 + 1）），那么当在最大周期中有100%个占空比，即PR2＝255时，如果CCPR1L＝255和CCP1CON位4和5＝11，那么两者都在最大值1023，那么它是1023 /（4＊（255＋1））＝w w。不是100%。公式中的分母不应该有-1吗？



      以下为原文

    Ok, thank you. I have one more question:
If the duty cycle is:

duty cycle = CCPR1L:CCPCON<5,4>/(4(PR2+1)), then when having 100% duty cycle at max period which is PR2 = 255, if CCPR1L = 255 and CCP1CON bits 4 and 5 = 11, then both together are at a max value of 1023, then it is 1023/(4*(255+1)) = 1023/1024 which isn’t 100%. Shouldn’t there be a -1 at the denominator in the formula?

1023/1024＝99.9%，大于100%。



      以下为原文

   
1023 / 1024 = 99.9% which is _not_ more than 100%.

是的，但还不到100%。分子和分母不匹配。



      以下为原文

    True, but it’s still not 100%. Numerator and denominator don’t match.

CCPR1L必须大于PR2以获得100%的占空比。使用PR2＝255, 100的占空比是不可能的。



      以下为原文

   
CCPR1L must be greater than PR2 to get 100% duty cycle.  With PR2 = 255, 100% duty cycle is not possible.

哦，是这样吗？因此，由于PR＝255是不可能得到100%的占空比，那么用PR2＝254，那么分母是1020，所以这就是我们需要设置CCPR1L和CPCPCON lt；4，5和gt；以及，得到1020/1020。如果分子仍然是1023，我们得到超过100%的占空比怎么办？



      以下为原文

    Oh, is that so. So since PR = 255 is impossible to get 100% duty cycle, then with PR2 = 254, then the denominator is 1020 so that’s what we need to set CCPR1L and CCPCON<4,5> to as well, to get 1020/1020. What if the numerator is still 1023 and we get more than 100% duty cycle?

如果你设置超过100%（当PR2小于255），那么PIN将保持高持续。如果你想得到100%当PR2是255，你必须特别检测该条件，并禁用PWM模块（并手动设置GPIO引脚高），只要你想它ReMA。在100%点钟。



      以下为原文

    I agree with 1and0.
If you set more than 100% (when PR2 is less than 255), then the pin will stay high continuously.
 
If you want to get 100% when PR2 is 255, you have to specially detect that condition, and disable the PWM module (and manually set the GPIO pin high) for as long as you want it to remain at 100%.

1。因为TMR2在下一个增量周期中被清除[113.1] 2（2）。他们是。检查方程11-2和11-3。它们都表示CCP1RL：CCP1CON＆LT；5:4和Gt；这是由Cbit 1CL寄存器和CCP1CON寄存器的位4和5组成的10位值：（CCP1RL和LT；2）*（（CCP1CON和GT和GT；4）和0x03）3。不知道你的意思。图11-3显示占空比寄存器为CCPR1L，仅次于CCP1CON/LT；CCPR1H是满10位、只读寄存器的“高”8位。它实际上并不表示这两个“低”侧位是什么，但大概它们是从CCP1CON＆LT；5:4和Gt内部加载的。占空比由一个由CPC1RL组成的10位值设置：CCP1CON＆LT；5:4和Gt，这是来自CCP1RL寄存器的8位值，该寄存器与CCP1CON寄存器中的两位相连（即CPC1RL寄存器左移两位，然后bitwise ORed从CCP1CON寄存器移位到两位），之后Y向右移动了4个位置，并掩蔽只包括那些位——就像上面我所展示的那样。也许你正在看一个旧的数据表。我正在看DS41262E。当您将一个值写入CCPR1L时，它被自动加载到CCPR1H中。SITECCPR1H是只读的，当文档引用ToCPR1H时，只知道必须编写ToCPR1L来影响更改（即使其工作）。CCPCP1CON寄存器的比特5和4仅是进程的一部分（仅为10位占空比确定值的2位）。要设置完整的10位，还必须设置CCPR1L值，假设它需要改变。这是一个必要的邪恶，使用8位处理器做非8位的东西，如使一个10位PWM模块的工作。换句话说，向CCPR1L的写入有效地写入CCPR1H。系统内部将CCPR1L值2位向左移位，然后将其写入10bit从寄存器（CCPR1H是其中的一部分）。BTW：您可以仅通过写入ToCPR1L来实现8位PWM特性，并且保持位5和A。MP（4）（CCP1CON寄存器）设置为零。比特5和4被放置在租赁的显著位置。它们增加了分辨率，而不限制这种多功能性。



      以下为原文

    1. Because TMR2 is cleared "on the next increment cycle" [11.3.1 ¶2]
2. They are.  Check out Equation 11-2 and 11-3.  They both indicate CCP1RL:CCP1CON<5:4> which is a 10bit value composed of both the 8bit CCP1RL register and bits 4 & 5 of the CCP1CON register:
 
(CCP1RL<<2) | ((CCP1CON>>4) & 0x03)
 
3. Not sure what you mean.  Figure 11-3 shows the Duty Cycle Registers as CCPR1L next to CCP1CON<5:4>.  CCPR1H is the "High" 8 bits of the full 10 bit, read only register.  It really doesn't indicate what the two "Low" side bits are, but presumably they are internally loaded from CCP1CON<5:4>.  The Duty Cycle is set by a 10 bit value composed of CCP1RL:CCP1CON<5:4> which is the 8 bit value from the CCP1RL register joined with the two bits from the CCP1CON register (i.e. the CCP1RL register is shifted left two bits, and then bitwise-ORed to the two bits from the CCP1CON register, after they are shifted 4 positions to the right and masked to include only those bits -- like i showed, above.

Perhaps you're looking at an old datasheet.  I'm looking at DS41262E.  

When you write a value to CCPR1L, it is automagically loaded into CCPR1H. Since CCPR1H is Read Only, when the documentation refers to CCPR1H, just know that one must write to CCPR1L to affect a change (i.e. make it work).  Bit 5 and 4 of the CCP1CON register are only part of the process (only 2 bits of the full 10 bit duty cycle determining value).  To set the full 10 bits, one must also set the CCPR1L value, assuming it needs changing.  This is a necessary evil of using an 8-bit processor to do non-8bit stuff, like make a 10 bit PWM module work.  In other words, writing to CCPR1L is effectively writing to CCPR1H.  The system internally shifts the CCPR1L value 2 bits to the left, before writing it to the 10bit Slave register (that CCPR1H is a part of).

BTW: you can implement an 8 bit PWM feature by merely writing to CCPR1L, and keeping bits 5 & 4 (of the CCP1Con register) set to zero.  bits 5 and 4 were put in the Lease Significant position for this very purpose.  They add resolution without limiting this versatility.