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你好！在我的项目中，我用USPEIC18F26K22（SOIC）在一个带有LCD、按钮和一些简单组件的单层面板上。虚幻环境是使用等离子逆变器（用于CNC操作）几米从我的面板。如果等离子逆变器启动（我认为强大的电流/电压产生EMP），我的板上的PIC18F26K22将重置。PIC面板由电池供电，不与任何其他设备连接。我还有一个带有类似功能的ATMEGA8A面板。这个面板不受“EMP”的影响，这项工作很好。我们试图屏蔽，使用更多的电容器，保护二极管，ButiN有效的面板。我的问题是：PIC架构对EMP（电磁骚扰）更敏感吗？这对我来说很不舒服。有人遇到过这样的问题吗？谢谢您！
以上来自于百度翻译 以下为原文 Hi! In my project, I use PIC18F26K22 (SOIC) on a single layer panel with LCD, buttons and some simple components. In real environment is used a plasma inverter (for CNC operations) a few meters from my panel. And if the plasma inverter started (I think the powerful current/voltage generate EMP), the PIC18F26K22 on my board will reset. The PIC panel powered by battery and no connection to any other device. And I have an other panel with ATmega8A with similar functions. This panel is not affected by "EMP", this work well. We tried to shield, ground the panel, using more capacitors, protection diodes, but ineffective. My question: it is possible the PIC architecture much more sensitive to EMP (electromagnetic disturbance) ? This is very uncomfortable for me. Has anyone encountered such a problem? Thank you! 
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11个回答
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“单层面板”是否意味着它是单面PCB？你能给我们看一下你的电路板的原理图吗？
以上来自于百度翻译 以下为原文 Does "single layer panel" mean it is a single sided PCB? Can you shows us a schematic of your board? |
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嗨，看一下数据表中的第4部分，看看是否可以使用该部分来缩小原因。
以上来自于百度翻译 以下为原文 Hi, Have a look at section 4.0 in the data sheet, see if you can use that section to narrow down the cause. |
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“单层面板”是否意味着它是单面PCB？只有一面有铜区域，但部件（SMD+TH）都是一边。我附上了面板的示意图，以及来自原型的照片。可能是EMP在铜轨道中引起的干扰…谢谢。
以上来自于百度翻译 以下为原文 Does "single layer panel" mean it is a single sided PCB? Only one side has the copper area, but components (SMD + TH) are both side. I attached the schematic of the panel, and a photo from prototype. Possibly the disturbance of EMP induced in the copper tracks... Thank you. Attached Image(s) |
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编辑：在原型面板右侧，你可以看到一些其他组件（SOIC8，二极管，两个LED……）。它们用于其他目的，它们没有在布线图中显示（但它们甚至没有连接到任何东西）。错误的视频：HTTPS://www. Youtub.com /表？V= PRVLNW1T14E
以上来自于百度翻译 以下为原文 edit: on the prototype panel right side you can see some other components (SOIC8, diodes, two LEDs...). They are there for other purposes, they are not shown in the wiring diagram (but they are not even connected to anything). Video of the error: https://www.youtube.com/watch?v=PrVlnW1T14E |
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嗨，尝试将连接到MCLR的R3更改为较低的值，47 K太高。在这种环境下，你可能需要使用1K电阻。先试试4.7K。
以上来自于百度翻译 以下为原文 Hi, Try changing R3 connected to MCLR to a lower value, 47K is too high. In that environment you may need to use a 1K resistor. Try a 4.7K first. |
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有可能PIC架构对EMPI更敏感，经常读取它非常健壮，而不是对EMP敏感。另一个面板上的轨迹有多紧凑？你对MCLR的跟踪真的很长。那会引起问题的！你已经建立了一个很好的天线。也许更小的R3会更好。试着把R3放在PIC附近，而不是在最后。你是如何做你的盾的？一个具有大GND区域的双/多层板应该有助于屏蔽。
以上来自于百度翻译 以下为原文 >>it is possible the PIC architecture much more sensitive to EMP I often read it is very robust and not that sensitive to EMP. How compact/how long are the traces on the other panel? Your trace for MCLR is really really long. That should cause problems!. You have build a nice antenna. And perhaps a smaller R3 would be better. And try placing R3 near the PIC and not at the very end. How have you done your shield? A double/multilayer PCB with big GND areas should help to shield, too... |
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MCLR功能被配置位禁用。这排除了MCLR上的长跟踪问题。或不是？其他想法：电源上的瞬态抑制器二极管（VDD-GND）引脚可以消除干扰？电路也被屏蔽了。（我没有尝试，但另一个人，不幸的是，我只能描述他的经验）。编辑：另一个小组（与AVR）比这小得多。
以上来自于百度翻译 以下为原文 MCLR function disabled by configuration bit. This excludes the problem of a long trace on MCLR ... or not? Other idea: Transient suppressor diode on power supply (Vdd - GND) pins can eliminated the disturbs? The circuit has been tried shielded too. (I did not try it out, but another person, unfortunately I can only describe his experiences). edit: the other panel (with AVR) much smaller than that. |
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No. MCLR也喜欢编程。通过PIC可以激活程序/验证模式，所以有必要注意如何线程MCLR引脚！这有助于不烧坏电路。问题是，接地是如何完成的？No.PCB，地面等离子体反相器，这不是PE…面板越大，痕迹越长。长的跟踪是非常糟糕的，因为它们作为天线，并且可能导致许多问题。
以上来自于百度翻译 以下为原文 No. MCLR is for programming, too. Throu EMV the PIC could activate the Program/Verify mode, so there is definitly to take care how to thread the MCLR pin! That could help not to grill your circuit. The question is, how was grounding done? GND of PCB, ground of PE ground of plasma inverter if that's not PE... The bigger the panel, the longer the traces. Long traces are very bad cause they act as antennas and that could cause many issues. |
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也许我错过了它，但我没有看到任何解耦上限的微观上的VDD。也许是一个0.1UF与220PF低ESR陶瓷平行。把它放在旁边的微型，所以导线长度不会影响这么多。另一个想法（可能我错过它），但你有没有重置电压设置太低的权力？也许检查板上的实际电压。还有，我建议你采取任何建议来抑制瞬态/噪声，使它成为一种累积的方法，直到它工作，然后看看你可以没有什么生活。
以上来自于百度翻译 以下为原文 Maybe I missed it, but I didn't see any decoupling caps on the micro on Vdd. Perhaps a 0.1uf in parallel with a 220pF low ESR ceramic. Put it RIGHT next to the micro so the lead-length doesn't impact so much. Another thought (again maybe I missed it), but do you have the power on reset voltage set too low? Perhaps check that against the actual voltage on the board. Also - I might suggest whatever suggestion you take for transient/noise suppression to make it a cumulative approach until it works, then see what you can live without. |
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不幸的是，我还不知道，BuTI会和这个人（谁测试我的小组）在这个话题上交谈。并测试这些步骤：-将MCLR电阻器更改为1K，如果没有EffETCT：-减少MCLR跟踪，如果没有效果：-尝试PIC在较小的PANELL上感谢所有的答案，我很快就能报告结果。
以上来自于百度翻译 以下为原文 Unfortunately, I don't know yet, but I will talk to the man (who tests my panel) in this topic. And test these steps: - change MCLR resistor to 1k, if no effetct: - reduction the MCLR trace, if no effect: - try PIC on smaller panel Thank you all for the answers, I will soon be able to report the results. |
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尝试添加一些额外的上限在VDD引脚关闭PIC。应该选择这些盖子以提供更宽的旁路。除了典型的0.1UF之外，我会在PIC的路径中直接推荐1UF和1000 PF。如果部分仍然复位，您可能需要查看所有的输入和输出设置为低，以确保没有对他们有负电流注入。把肖特基二极管钳位在任何受影响的引脚上。
以上来自于百度翻译 以下为原文 Try adding some additional caps on the Vdd pin close the PIC. These caps should be chosen to provide wider bypass. In addition to the typical 0.1uF, I would recommend a 1uF and a 1000pF directly in the path to the PIC. If the part still resets you may need to look at all the input and outputs set low to make sure none on them have negative current injection. Put schottky diode clamps on any pins that are effected. |
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