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我使用MPLABX 4.10和XC32 2.05的和声2.05 -所有的最新的东西——在一个以PIC32 MZ2048 EFH144为目标的项目上进行最后的润色。我发现了一个关于连贯(非缓存)内存分配的问题。下面是内存声明的源代码行:Uti32IbTeTyx((相干,对齐(32)))CAN0FIFODATA(16×2×4);UIT32 32×T2属性((相干,对齐(32)))CAN1FIFODATA(1×4×4);它们是用于接收CAN消息的512字节和64字节缓冲器。这里是MAP文件的连贯部分,后面是缓存段的第一行:SDS$0xA000 07AF0 0x450BuffxBA077AF00X4000构建/PIC32μMZYRVY5/生产/OXTEX/DRVVYNVM .O 0xA000 07AF0 GDRVNVMELASE缓冲区*填充*0xA000 0BAF0 0x10. BSS.CAN0FIFODATA.CAN0FIFODATA 0XA000 0BB00 0X200构建/PIC32×MZYRVY5/生产/Ext/ 1451566645 /PIC320xAA000 0BB00 CAN0FIFODATA。BSS.GSISFSFMIDABUFFER。GXSFSF0BD00 0x200构建/PIC32μMZYRVY5/生产/OXEXFSMIATAAL管理器。0SXA000 0BD00 GSISFSFMIATABUFER。BSS.CAN1FIFODATA CAN1FIFODATA 0XA000 0BF00 0X40构建/PIC32O.Rev5.5/生产/XEX/5/PIC32 MZCAN CAN .0xA000 0BF00 CA1FIFODATA.BSS 0X800 0BF30 0x10000 . BSS 0x800 0BF30 0x10000构建/PIC32×MZYRVY5/生产/Ext//EX/HEAP4.4协议(CAN1FIFODATA的大小为0x40(正确)),应占用0xA000 0BF00 tHRAW 0xA000 0BF3F,但是HeAPS4.0节开始于0x800 0BF30。有16字节的重迭!这里发生了什么事?
以上来自于百度翻译 以下为原文 I am using HARMony 2.05 with MPLABX 4.10 and xc32 2.05 - all the latest stuff -- to put the finishing touches on a project that targets the PIC32MZ2048EFH144. I have discovered an issue with coherent (non-cached) memory assignments. Here are the source lines for the memory declaration: uint32_t __attribute__((coherent, aligned(32))) CAN0FifoData[16*2*4]; uint32_t __attribute__((coherent, aligned(32))) CAN1FifoData[1*4*4]; They are 512 and 64 byte buffers used to receive CAN messages. Here is the coherent section of the map file followed by the first couple of lines of the cached section: .COHERENTBSS$ 0xa0007af0 0x4450 .COHERENTBSS$ 0xa0007af0 0x4000 build/PIC32_MZ_Rev_5/production/_ext/1742787907/drv_nvm.o 0xa0007af0 gDrvNVMEraseBuffer *fill* 0xa000baf0 0x10 .bss.CAN0FifoData.CAN0FifoData 0xa000bb00 0x200 build/PIC32_MZ_Rev_5/production/_ext/1451566645/pic32MZ_can.o 0xa000bb00 CAN0FifoData .bss.gSYSFSMediaBuffer.gSYSFSMediaBuffer 0xa000bd00 0x200 build/PIC32_MZ_Rev_5/production/_ext/127447246/sys_fs_media_manager.o 0xa000bd00 gSYSFSMediaBuffer .bss.CAN1FifoData.CAN1FifoData 0xa000bf00 0x40 build/PIC32_MZ_Rev_5/production/_ext/1451566645/pic32MZ_can.o 0xa000bf00 CAN1FifoData .bss 0x8000bf30 0x10000 .bss 0x8000bf30 0x10000 build/PIC32_MZ_Rev_5/production/_ext/1412655874/heap_4.o Notice that the size of CAN1FifoData is 0x40 (which is correct) and should occupy 0xa000bf00 through 0xa000bf3f, but the heap_4.o section starts at 0x8000bf30. There is an overlap of 16 bytes! What is going on here? |
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7个回答
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XC32 2.05 -所有最新的填充不是一个版本。AN不应该使用XC32的最新版本。你应该使用你的和声所说的版本来使用。
以上来自于百度翻译 以下为原文 xc32 2.05 - all the latest stuff That is not a version. An you should not be using the Latest version of XC32. you should be using the Version that your version of harmony says to use. |
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乞求不同……C:程序文件(x86)Microchip xC32 v2.05bin xC32 gcc.exe……是推荐使用和声2.05的版本。
以上来自于百度翻译 以下为原文 Beg to differ... "C:Program Files (x86)Microchipxc32v2.05binxc32-gcc.exe" ...is the version recommended to use with Harmony 2.05 |
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先生,你说得对。但是,在使用MPLAB协调之前,http://WW1.Microchip .com/下载/ En/DeVicoOC/MPLAB %/20%Ornal%20%发布%20V2.05.PDFPIP3软件要求:确保MPLAB X IDE V4.05MPLAB XC32 C/C++编译器V1.44与V1.44(B)部分支持PATCH安装MPLAB和谐配置器V2.0.5.2您应该使用V1.44。试试看这个问题是不是固定的,因为和睦并不总是最好的。确保你有正确的MHC版本。
以上来自于百度翻译 以下为原文 You are correct sir. They did a big jump. But: http://ww1.microchip.com/downloads/en/DeviceDoc/MPLAB%20Harmony%20Release%20Notes%20v2.05.pdf Page 3 Software Requirements Before using MPLAB Harmony, ensure that the following are installed: • MPLAB X IDE v4.05 • MPLAB XC32 C/C++ Compiler v1.44 with v1.44(B) part support patch installed • MPLAB Harmony Configurator v2.0.5.2 You should be using V1.44. Try that and see if the issue is fixed. For Harmony Newest is not always best. And insure you have the correct version of MHC. |
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我试过XC32 V1.44,V1.43,最后V1.42。1.44和1.43产生相同的结果。1.42是完全不同的(正确的,我想)。注意:我已经改变了CAN1FIFODATA缓冲区大小从64(0x40)到96(0x60)字节,以允许在V2.05中正确地工作,这是在下面的大小。这里是V1.42:0x800 1FB20 WebStrug5.BSS.CAN1FIFODATA CAN的MAP输出。1SIFO数据0xAA1FF400x60.BSS.FANODATA.0xAA1FB400x60Bug /PIC32μMZYRVY5/生产/OXEX/PIC32 MZZCAN CAN .0xAA1FB40 CAN1FIFODATA .数据0x800 1FBA0 0x50 .数据0X800 1FBA0 0X50 Bug /PIC32μMZYRVY5/生产/OXEX/1402959948/SythyIn .0x800 1FBA0 TCPIPHEAPCONTIVE通知,与其创建一个连贯的部分,它只需从0x8更改地址(正确地通过方式)…它被缓存到0xA…这是不缓存的。所以,这个问题似乎已经在V1.43中出现了。我会回去阅读这个版本的发行说明,看看是否能找到连贯性的东西。
以上来自于百度翻译 以下为原文 I tried XC32 v1.44, v1.43 and finally v1.42. 1.44 and 1.43 produced the same results. 1.42 was quite different (and correct, I think). Note: I have changed the CAN1FifoData buffer size from 64 (0x40) to 96 (0x60) bytes to allow things to work correctly in v2.05 and that is shown in the size below. Here is the the map output from v1.42: 0x8001fb20 webString5 .bss.CAN1FifoData.CAN1FifoData 0xa001fb40 0x60 .bss.CAN1FifoData.CAN1FifoData 0xa001fb40 0x60 build/PIC32_MZ_Rev_5/production/_ext/1451566645/pic32MZ_can.o 0xa001fb40 CAN1FifoData .data 0x8001fba0 0x50 .data 0x8001fba0 0x50 build/PIC32_MZ_Rev_5/production/_ext/1402959948/system_init.o 0x8001fba0 tcpipHeapConfig Notice that rather than creating a COHERENT section, it just changes the address (correctly by the way) from 0x8... which is cached to 0xa... which is non-cached. So, the problem seems to have crept in with v1.43. I will go back and read the release notes for that version and see if I can find anything about COHERENT. |
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这是一个你可能想在XC32论坛上发表的问题,或者把它放在一个支持票中。在过去,使用一个更新版本的编译器比一个被测试的和声有问题。请注意。
以上来自于百度翻译 以下为原文 It is an issue you may want to cross post to the XC32 forum, or put in a Support Ticket. In the past there have been issue with using a newer version of the compiler than the one the tested Harmony with. Be aware. |
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在V1.43版本的注释中,有关于连贯性的注释:“改进的连贯性属性——链接器现在将所有相干性属性变量组合在一起,并将它们对齐在缓存行边界上。”和“分配给L1缓存内存的变量——对于具有L1数据缓存的设备来说,数据变量是现在分配给KSG0数据存储区域(KSeG0XDATAYMEM),使其通过L1高速缓存访问。同样,分配堆和堆栈的链接器被分配给KSGE0区域。有一个新的CONTRONTROUNT变量属性,允许您创建分配给KSG1YDATAAYMEM区域的DMA缓冲区。未签名的int It-属性(缓冲)缓冲区[1024 ];当将CooHeTrn属性与ADDR结合时请务必使用设备的默认数据存储区域地址。在具有L1数据缓存的设备上,默认的数据存储区域是KSeG0xDATAYMEME。未签名的INTIN AtItEthyTy((相干,地址(0x800 01000)))缓冲器〔1024〕;“Notes使用“地址”参数,而不是仅使用我正在使用的对齐方式。UTPUT似乎解决了这个问题。我只是不喜欢我的代码中硬编码的RAM地址。
以上来自于百度翻译 以下为原文 There are comments in the v1.43 release notes about COHERENT. "Improved coherent attribute -- The linker now groups all coherent attributed variables together and aligns them on a cache-line boundary." and "Variables allocated to L1 cached memory -- For devices featuring an L1 data cache, data variables are now allocated to the KSEG0 data-memory region (kseg0_data_mem) making it accessible through the L1 cache. Likewise, the linker-allocated heap and stack are allocated to the KSEG0 region. There is a new coherent variable attribute that allows you to create a DMA buffer allocated to the kseg1_data_mem region. unsigned int __attribute__((coherent)) buffer[1024]; When combining the coherent attribute with the address attribute, be sure to use the default data-memory region address for the device. On devices featuring an L1 data cache, the default data-memory region is kseg0_data_mem. unsigned int __attribute__((coherent,address(0x80001000))) buffer[1024];" The notes use the "address" parameter with coherent rather than just the alignment that I was using. I experimented with address, and the output seems to solve the problem. I just don't like hard coded RAM addresses in my code. |
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