如何减少或消除设计中的拥塞

嗨，
尝试拥堵策略。
您可以通过布局规划来缓解路由拥塞和时序问题，以防止逻辑在实施期间被置于关键或拥塞区域。
有关详细信息，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug938-vivado-design-analysis-closure-tutorial.pdf的第44页。
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
Try congestion stratagies as well.
 
You can alleviate routing congestion and timing issues by floorplanning to prevent logic from
being placed into critical or congested areas during implementation. Refer to page 44 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug938-vivado-design-analysis-closure-tutorial.pdf for details.
 
Thanks,Vijay
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嗨，
你尝试过不同的实施策略吗？



以下为原文

 
Hi,
 
Did you try with different implementation strategies?

是的，我尝试FlowRuntime优化但效果不大



以下为原文

yes i tried FlowRuntime optimized but little effect

嗨，
尝试拥堵策略。
您可以通过布局规划来缓解路由拥塞和时序问题，以防止逻辑在实施期间被置于关键或拥塞区域。
有关详细信息，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug938-vivado-design-analysis-closure-tutorial.pdf的第44页。
谢谢，维杰-----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Hi,
Try congestion stratagies as well.
 
You can alleviate routing congestion and timing issues by floorplanning to prevent logic from
being placed into critical or congested areas during implementation. Refer to page 44 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug938-vivado-design-analysis-closure-tutorial.pdf for details.
 
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.