在地点和路线阶段发出ISE警告

丢失的数据文件是安装问题或环境设置问题。
布雷特



以下为原文

A missing data file is either an install issue or a problem with your environment settings.
 
Bret

感谢您的回复。
我是ISE设计套件的新手。
在布局和布线阶段，我收到了警告信息
“在布局器数据文件中找不到PLACE全局时钟IO数据”....
即使我收到了上述警告信息，我也成功实施了RTC。
那么，上面的警告信息到底是什么？
请帮帮我吗？



以下为原文

Thanks for your reply.
 
I am new to ISE design suite.
I have got the warning message during place and route phase is
"PLACE global clock IO data is not found in the placer data files"....
 
even though i have got the above warning message, i have succesfully implemented the RTC.
 
So, what exactly above warning message is indicating?
 
please help me in this?

如果您可以提供包含消息ID号的完整消息文本，我可以进行搜索以查看之前是否已经看过它。
布雷特



以下为原文

If you can provide the full message text including the messages ID number I could do a search to see if it's been seen before.
 
Bret

嗨布雷特，
这是为spartan3 fpga（celoxica RC10）编写的代码
// ------------------------------------------------
---------------------------------------
模块计数器（输入线clk_i，输入线reset_n，输出线[2：0] count_out）;
reg [2：0] count_nxt;
始终@（posedge clk_i或negedge reset_n）if if（！reset_n）begin count_nxt end else else begin count_nxt end end assign count_out = count_nxt;
endmodule
// ------------------------------------------------
--------------------------------
RC10板的UCF文件
#PACE：开始PACE I / O引脚分配NET“clk_i”LOC =“N10”; NET“count_out [0]”LOC =“D2”; NET“count_out [1]”LOC =“D3”; NET“count_out [
2]“LOC =”E2“;
// ------------------------------------------------
----------------------
综合警告信息
警告：LIT：243  - 逻辑网络N4无负载。警告：LIT：395  - 重复上述警告消息base_net_load_rule 1
警告：放置 - 在设备的布局器数据文件中找不到全局时钟IO数据。
请提供解决方案



以下为原文

Hi Bret,
 this is the code written for spartan3 fpga (celoxica RC10)
 
//---------------------------------------------------------------------------------------
module counter(
input wire clk_i ,
input wire reset_n,

output wire [2:0] count_out
);
reg [2:0] count_nxt;

always @(posedge clk_i or negedge reset_n) begin
if (!reset_n) begin
count_nxt <= 'd0;
end
else begin
count_nxt <= count_nxt+1'b1;
end
end

assign count_out = count_nxt;
endmodule
 
//--------------------------------------------------------------------------------
 
UCF file for RC10 board
 
#PACE: Start of PACE I/O Pin Assignments
NET "clk_i" LOC = "N10" ;
NET "count_out[0]" LOC = "D2" ;
NET "count_out[1]" LOC = "D3" ;
NET "count_out[2]" LOC = "E2" ;
 
 
//----------------------------------------------------------------------
synthesis warning messages
 
WARNING:LIT:243 - Logical network N4 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
WARNING:Place - Global Clock IO data not found in placer data files for device .
 
 
Please provide the solution