有没有人成功创建过使用VSC8541以太网PHY的设计？

@ thoma***1936我确实和我的工程师说话，他创建了SmartFusion 2 Maker-Board Wiki，不幸的是他没有在他的项目中使用以太网做任何工作。
我已将您的帖子转发给我的产品经理，以了解他是否对MicroSemi有任何见解或进一步的信息。



以下为原文

        @thoma***1936 I did speak to my engineer who created the SmartFusion 2 Maker-Board Wiki and unfortunately he did not do any work with ethernet on his project. I have forwarded your post to my product manager to see if he has any insight or further information from MicroSemi.

我解决了它，有人可能想要将细节添加到维基。
电路板正确配置50 MHz外部时钟的两个时钟选择输入（我多次检查）。
哪个是REFCLK_SEL0为低电平且REFCLK_SEL1为高电平，它通过10K上拉/下拉来实现这一点。
我在数据手册的细则中发现，内部它们都被拉大约30k，因此拉低的输入在地面上方徘徊约0.6V。
这个数字很高。
该芯片认为它具有125MHz时钟而不是50MHz时钟，并且它无法自动协商链路。
通过使用FPGA主动将两个时钟选择输入驱动到正确的电平来修复它。
为了获得芯片，您无法依靠板上拉或使用内部FPGA上拉。
必须驱动输入。
也许在未来的电路板修改中将下拉变为1K或者将其全部省略。



以下为原文

        I solved it and someone may want to add the details to the wiki.
The board correctly configures the two clock selection inputs for a 50 MHz external clock (I checked this many times). Which is REFCLK_SEL0 low and REFCLK_SEL1 high and it does this with 10K pull ups/downs. What I discovered in the fine print of the data sheet is internally they are both pulled up with roughly a 30k so the input that is pulled low is hovering about 0.6V above ground. Which counts as a high. The chip thinks it has a 125MHz clock instead of the 50MHz clock and it can’t auto negotiate a link. Fixed it by actively driving both clock select inputs to the correct level with the FPGA.
To get the chip up you cant count on the board pull up or use an internal FPGA pull up. The inputs must be driven. Maybe on future revisions of the board change the pull down to 1K or omit it all together.

嗨托马斯，
也许你几乎无法描述你正在运行的软件，我找不到任何关于这个PHY的教程，即microsemi
固件目录以太网项目不支持此phy，
非常感激任何的帮助
谢谢
康拉德



以下为原文

        Hi Thomas,
Maybe you can describe little what software you are running, I cant find any tutorial for this PHY, the microsemi
Firmware catalog ethernet project dont have support for this phy,
Any help would be most appreciated
Thanks
Konrad