当MAP进入阶段10.8时分频器就会挂断

嗨本，
你可以花一分钟时间用几句话描述你是怎么做到的，比如说
1.在vivado下生成分隔符
2.启动sysgen ??
sysgen是一个独立的工具吗？
2.1安装sysgen ???
3.启动sysgen ...
4.导入文件分隔符。??
5. sysgen的输出......？
6.使用文件??
在ISE
谢谢
亨氏



以下为原文

Hi Ben,
could you spend a minute and describe in a few sentences how you did this, like
 
1. generate the divider under vivado 
2. start sysgen  ?? is sysgen a stand alone tool ?
2.1 install sysgen ???
3. start sysgen ...
4. import file  divider.??  
5. output of sysgen ... ?
6. use file ??   in ISE
 
Thanks
Heinz

你好
如果您的目标设备是virtex6，则无法使用vivado。
5系列和6系列设备的唯一解决方法是使用除1之外的每分钟时钟选项。
仅当分频器核心中的每分频时钟选项设置为1时才会出现此问题。
有关使用此工具进行系统生成和设计的更多详细信息，请参阅以下链
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug897-vivado-sysgen-user.pdf
问候，萨蒂什-----------------------------------------------
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- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
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以下为原文

Hi
 
You cannot use vivado if your target  device is virtex6.
 
The only workaround for 5 and 6 series devices is to use the clock per division option other than 1.
 
As this issue is seen only when the clocks per division option is set to 1 in the divider core.
 
Refer below links for more details about system generator and design with this tool
 
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug897-vivado-sysgen-user.pdf
Regards,

Satish

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谢谢，我的设备是zynq



以下为原文

Thanks, my device is zynq

hbair，
如果您使用Zynq，则必须使用Vivado。
此错误已在Vivado中修复，因此您应该能够生成并使用您想要的任何分隔符！
本



以下为原文

hbair,
 
If your using the Zynq then you will have to use Vivado. This bug has been fixed in Vivado so you should be able to generate and use any divider you want!
 
Ben

非常感谢，但是我知道我使用ISE 14.7和Zynq xc7z045非常成功。
PCIE dma，很多图像处理/过滤器，我开始将项目导入Vivado，这将花费我一段时间.Vivado中的问题始于下载电缆:(，所以短期内我会希望继续使用ISE
，但是在Vivado.Anyway中生成的分隔符，这对我帮助很大。



以下为原文

Thanks a lot, but right know I use ISE 14.7 with Zynq xc7z045
very successful. PCIE dma, a lot of image processing/filters,
I started importing the project into Vivado, that will take me a while.
Problems in Vivado started with the download cable :(,
So for the short term I would have liked to continue with ISE, but with the divder generated in Vivado.
Anyway, this all helped me a lot.

这个错误在14.7中挂起了我的映射。
该设计适用于zynq。
这会被修复还是掉线？



以下为原文

This bug hanged my mapping in 14.7.
 
The design is for a zynq. Will this ever be fixed or is the bug dropped?

我也挂了，尝试将地图Placer Effort Level设置为标准。
这帮助了我。
我花了3个小时来绘图，



以下为原文

Mine hang too,  try to set the map  Placer Effort Level to standard.  That helped me. I took 3 hours to map, 

目前，重点是解决Vivado中的问题。
因此，Vivado的采用有很大的推动力。
但是如果设计在ISE中挂起并且没有可以解决此问题的开关，请随时告诉我们。
我们很乐意提供帮助。
问候
Sikta



以下为原文

Currently the focus is to fix issues in Vivado. Hence there is a lot of push for Vivado adoption.
But please feel free to let us know if design hangs in ISE and there is no switch that helps workaround this.
 
We will be glad to help.
 
Regards
Sikta

你好
这对于ISE尚未修复，解决方法是将每分钟时钟值设置为1以外的值。
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
This is not yet fixed for ISE,the workaround is to use clock per division value set to values other than 1.
Regards,

Satish

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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