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嗨,大家好,
只是一个简单的问题。 FPGA编辑器是否有限制为包含嵌入式处理器(如PowerPC)的设计生成比特流? 我问的原因是因为我在Project Navigator中创建了一个设计并运行了PAR。 然后我在FPGA编辑器中打开放置和布线设计,并尝试从那里创建比特流。 但是,我只是收到错误,无法生成比特流。 没有其他理由。 我使用的是ISE 14.7和Virtex-5 FPGA。 以上来自于谷歌翻译 以下为原文 Hi guys, Just a quick question. Is there a limitation on FPGA editor to generate a bitstream for a design containing an embedded processor, such as a PowerPC? The reason I am asking is because I've created a design in Project Navigator and ran the PAR. I then opened the placed and routed design in FPGA editor and tried to create the bitstream from there. However, I simply receive an error the bitstream couldn't be generated. No other reason was given. I am using ISE 14.7 and a Virtex-5 FPGA. |
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16个回答
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我为延迟回应道歉。
我遇到了一些与项目有关的其他非相关问题,最近才解决了我在这个帖子中遇到的问题。 显然,问题源于顶层设计中需要的“edkBmmFile.bmm”,才能生成比特流。 将ncd保存到新位置并将“edkBmmFile.bmm”复制到同一位置后,成功生成了比特流。 当我尝试从命令行生成相同的比特流时,我偶然发现了这一点。 错误更加清晰。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 I apologize for the delay in response. I ran into some other non-related issues with the project and only recently solved the problem I had in this thread. Apparently the issue originated from "edkBmmFile.bmm" that was required from the Top Level design, before the bitstream could be generated. After saving the ncd to the new location and copying "edkBmmFile.bmm" to the same location, the bitstream was succesfully generated. I stumbled upon this when trying to generate the same bitstream from command line. The error was much clearer. View solution in original post |
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R,
该设备是否针对FX设备? 哪一个? Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 r, Is the device targeted a FX device? Which one? Austin Lesea Principal Engineer Xilinx San Jose |
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确切的错误是什么?
Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 What is the exact error? Austin Lesea Principal Engineer Xilinx San Jose |
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我只是想澄清一下,ISE能够创建没有任何错误的比特流。
我已将路由的ncd文件保存在不同目录中的项目中。 如果我在FPGa编辑器中打开它,我只是得到一个错误:“bitgen命令无法写入.bit文件。” 而已。 没有其他错误或警告。 考虑到ISE能够生成比特流,并且如果FPGA编辑器没有限制为包含嵌入式处理器的项目创建bitream,我会认为在比特流之前ncd文件需要一些其他文件(或其他东西) 被创造。 我的假设是否正确? 以上来自于谷歌翻译 以下为原文 I just want to clarify the ISE is able to create the bitstream without any errors. I have saved the routed ncd-file from a project in a different directory. If I open that in FPGa editor, I simply get an error: "The bitgen command failed to write the .bit file." That's it. No other errors or warnings. Considering that ISE is capable of generating the bitstream, and if FPGA editor has no limitation on creating the bitream for a project containing an embedded processor, I would think some other file (or something) is required with the ncd-file before the bitstream can be created. Am I correct in my assumption? |
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R,
ncd文件应包含FPGA_Editor创建位或bin文件所需的所有内容。 可能有数据进入BRAM中的.bmm文件,因此要使用它,您可能需要更多文件,但要创建比特流,它们不是必需的。 如果在您的设计中使用BRAM,要创建一个可以正常运行并按照您的需要运行的比特流,您将需要BRAM内容文件。 您是否为位文件指定了有效名称? (检查名称是否包含允许在名称中使用的字符)。 你能打开FPGA_Editor,什么都不做,写一个(空的)ncd文件,回去读取那个ncd文件,写一个比特流? 即使它是空的,它也应该创建一个有效的比特流,可以下载到设备上(DONE将变高),它将不再是其他任何东西。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 r, The ncd file should contain everything required for FPGA_Editor to create a bit or bin file. There may be data that goews into BRAM which is in .bmm files, so for it to work, you may need more files, but to create a bitstream, they are not required. To create a bitstream that ctually works and does what you want, you will need the BRAM content files, if BRAM are used in your design. Are you specifying a valid name for the bitfile? (check that the name has characters that are allowed to be used in a name). Can you open FPGA_Editor, do nothing at all, write a (empty) ncd file, go back and read in that ncd file, and write a bitstream? Even though it is empty, it should create a valid bitstream, that may be downloaded to the device (DONE will go high) and it will fo nothing else. Austin Lesea Principal Engineer Xilinx San Jose |
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嗨奥斯汀,
我尝试在与失败的目录相同的目录中创建一个空的ncd,并成功创建了bitsream。 所以我尝试了几个不同的东西。 我在ISE中重新打开了原始设计,并从此处重新打开了FPGA编辑器中的路由设计。 然后我将ncd文件保存到另一个目录,并立即尝试创建成功完成的比特流。 但是,如果我关闭所有内容并在FPGA编辑器中打开ncd文件,则bitgen会失败。 以上来自于谷歌翻译 以下为原文 Hi Austin, I tried creating the an empty ncd in the same directory as the one the failing, and the bitsream was sucessfully created. So I tried a couple of different things. I reopened the original design in ISE and reopened the routed design in FPGA editor from here. I then saved the ncd file to a different directory and immediately tried creating the bitstream, which completed successfully. However, If I close everything and open the ncd file in FPGA editor, bitgen fails. |
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嗨,
在失败的ncd中,您可以在FPGA编辑器中运行DRC - >工具 - > DRC - >运行并查看是否有任何警告? --Hem -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 Hi, In the ncd that is failing, can you run DRC in FPGA Editor --> Tools --> DRC --> Run and see if there are any warnings? --Hem ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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嗨哼,
如果我运行DRC,我有1156个警告和0个错误。 警告主要是针脚不会驱动设计中的任何负载。 但是,我不认为这是导致问题的原因。 如果我从ISE打开FPGA编辑器,保存设计,运行DRC然后生成比特流,我得到完全相同的警告数量并生成比特流。 以上来自于谷歌翻译 以下为原文 Hi Hem, If I run DRC, I have 1156 warnings and 0 errors. The warnings are mostly pins not driving any load in the design. However, I don't think that is what's causing the issues. If I open FPGA editor from ISE, save the design, run DRC and then generate the bitstream, I get exactly the same amount of warnings and the bitstream is generated. |
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你好
如果我正确理解了这个问题,那么当您从ISE调用FPGA编辑器时,会成功生成比特流。 如果你使用在par目录中生成的相同的ncd,然后在FPGA EDITOR STANDLONE中加载,它会失败, 您是否正在使用FPGA编辑器编写或保存ncd? 问候 Sikta 以上来自于谷歌翻译 以下为原文 Hi If I understand the issue correctly, bitstream is generated succesfully when you are invoking FPGA editor from ISE . If you use the same ncd thats generated in par directory and then load in FPGA EDITOR STANDLONE, it fails, Are you using to write or save the ncd from FPGA editor? Regards Sikta |
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嗨西卡,
是的,情况确实如此。 最后我想在FPGA编辑器中做一些更改,但是现在,我只打开ncd并点击bitgen。 以上来自于谷歌翻译 以下为原文 Hi Sikta, Yes, that is indeed the case. Eventually I would like to make some changes in FPGA editor, but for now, I only open the ncd and click on bitgen. |
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嗨,
我只能用BIST设计的例子重现这一点。 问题是由于bitgen的其他选项。 只需从窗口中删除它们即可。 如果你想覆盖你的位文件,只需要-w然后你应该能够通过FED成功生成比特流。 添加屏幕截图供您参考。 希望这可以帮助。 问候 Sikta 以上来自于谷歌翻译 以下为原文 Hi, I was just able to reproduce this with a example BIST design. The problem is due to the other options for bitgen. Just remove them from the window. If you want to override your bit file, just have -w and then you should be able to generate bitstream succesfully through FED. Adding the screenshot for your reference. Hope this helps. Regards Sikta |
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感谢Sikta的努力!
非常欣赏它。 但是,我没有其他bitgen选项。 我想还有一些我不知道的东西。 以上来自于谷歌翻译 以下为原文 Thanks for the effort Sikta! Much appreciate it. However, I don't have other bitgen options. I guess there is something else I am missing. |
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打开FED并放置并路由ncd,pcf并更改模式以进行读写。
我在ISE 14.7中运行它。 问候 Sikta 以上来自于谷歌翻译 以下为原文 Opened FED with placed and routed ncd , pcf and changed the mode to read and write. I am running this in ISE 14.7. Regards Sikta |
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@rikusleroux
您是否尝试过相同的步骤?请更新。 问候 Sikta 以上来自于谷歌翻译 以下为原文 @rikusleroux Did you try with the same steps?Kindly update. Regards Sikta |
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我为延迟回应道歉。
我遇到了一些与项目有关的其他非相关问题,最近才解决了我在这个帖子中遇到的问题。 显然,问题源于顶层设计中需要的“edkBmmFile.bmm”,才能生成比特流。 将ncd保存到新位置并将“edkBmmFile.bmm”复制到同一位置后,成功生成了比特流。 当我尝试从命令行生成相同的比特流时,我偶然发现了这一点。 错误更加清晰。 以上来自于谷歌翻译 以下为原文 I apologize for the delay in response. I ran into some other non-related issues with the project and only recently solved the problem I had in this thread. Apparently the issue originated from "edkBmmFile.bmm" that was required from the Top Level design, before the bitstream could be generated. After saving the ncd to the new location and copying "edkBmmFile.bmm" to the same location, the bitstream was succesfully generated. I stumbled upon this when trying to generate the same bitstream from command line. The error was much clearer. |
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