映射中的致命错误：检测到无效的合并操作

大家好，
我正在使用带有补丁的ISE 14.1，目标是Virtex-5。
在我的设计中有一个经典的双FF时钟域交叉电路，我想约束两个不同时钟域之间的路径，即第一个域的输出FF，以及第二个域的两个FF中的第一个FF的输入
域。
我已经进行了逻辑优化和注册重新定时，高正常工作，所有其他优化都关闭了。
一旦物理合成打开，映射错误就会出现以下消息：
FATAL_ERROR：时序：DoodleSubExperiment.c：872：1.35  - 检测到无效的合并操作：0x0  - > 0xfefefeff进程将终止。
这是什么？！
在添加约束之前没有发生这种情况......没有逻辑优化，这种方法很好，并且没有看到错误。
此外，什么样的源文件名是DoodleSubExperiment.c无论如何???



以下为原文

Hi all,

I'm using ISE 14.1 with patch, targeting a Virtex-5. In my design there is a classic double-FF clock domain crossing circuit, and I wanted to constrain the path between the two different clock domains, i.e. output FF of the first domain, and input of the FF for first of two FFs of the second domain. I've got logic optimization and register retiming turned on, effort at high-normal, all other optimiziations turned off.

As soon as physical synthesis turns on, Map errors out with the following message:
FATAL_ERROR:Timing:DoodleSubExperiment.c:872:1.35 - Invalid merge operation detected: 0x0 -> 0xfefefeff     Process will terminate. What is this?! This was not happening before I added the constraint... Without logic optimization this works fine and above error is not seen.

Besides, what kind of source file name is DoodleSubExperiment.c anyway???