[问答]

为什么在与VCC连接时最小化接地信号？

问答对人有帮助，内容完整，我也想知道答案 0 嗨，我对逻辑设计很陌生，如果我错过了一些明显的东西或者做了一些愚蠢的事情，那么对我来说很陌生，任何帮助都会非常感激。我已经在ISE 12.1中开始了一个简单的原理图设计（我知道原理图设计不是设计逻辑的好方法，但我会在学习语言时用VHDL重写设计）。该设计正在进行仿真，但据我所知，它不适用于拟合后仿真。在拟合后仿真中有太多的信号可以很好地处理正在发生的事情。我有一个Digilent XC2XL和CoolRunner-II入门套件，我开始尝试在XC9500XL器件上实现该设计。以下是我遇到的问题我遇到的问题.1）我在原理图中将网络绑定到VCC，当我实现设计时，我收到以下警告。 “警告：Cpld：828 - 信号'Status0Out.RSTF'已被最小化为'GND'。” 为什么在与VCC连接时最小化接地信号？附件是我设计部分的图片，此警告也适用于“StatusReg”组件.2）我在设计中触发了非同步时钟输入信号边缘的许多锁存器和其他组件。由于没有为这些触发信号分配时序约束，编译器对我大吼大叫。警告：Cpld：310 - 由于以下原因之一，无法应用tiMESPEC TS1002 = PERIOD：PERIOD_RD_N：0.000 nS：（a）未找到信号名称; （b）由于优化而删除或重命名的信号; （c）TIMESPEC中的FROM节点和TO节点之间没有路径。当我进入约束编辑器时，它希望我为时钟分配一个周期和占空比，但由于它是一个异步边沿触发器，我想把它分配给它？3）设计主要是异步的，并且有一个同步时钟用于一些组件。当我运行后拟合模拟时，许多异步信号不会改变，直到我为一个同步时钟输入信号计时，该信号不依赖于设计的任何这些组件。我试图取消选中“使用全局时钟”选项而不做任何更改。请提前获取任何帮助！编辑：右键单击图像并选择查看图像以查看其完整大小（firefox）或将其保存到桌面然后打开它。编辑2：下面的附件不是完整的设计。以上来自于谷歌翻译以下为原文 Hi, I am very new to logic design so bare with me if I am missing something obvious or doing something stupid, any help would be much appreciated. I have started a simple schematic design in ISE 12.1 (I know schematic designs are not a good way to design logic but I will rewrite the design in VHDL as I learn the language). The design is working in simulation but from what I can tell it does not work post-fit simulation. There are far too many signals in the post-fit simulation to get a good handle on what is going on. I have a Digilent XC2XL and CoolRunner-II starter kit, and am starting with trying to implement the design on a XC9500XL device. Here are the questions I have problems I am running into. 1) I have tied a net to VCC in the schematic and when I implement the design I get the following warning. "WARNING:Cpld:828 - Signal 'Status0Out<0>.RSTF' has been minimized to 'GND'." Why is minimizing the signal to ground when it is tied to VCC? Attached is a picture of the part of my design this warning applies too and inside the "StatusReg" component. 2) I trigger many of the latches and other components in the design on edges of inputs signals that are not synchronous clocks. The compiler is yelling at me for not assigning timing constraints to these trigger signals. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1002 = PERIOD:PERIOD_RD_N:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. When I go into the constraints editor it wants me to assign a period and duty cycle for the clock but since it is an asynchronous edge trigger what am I suppose to assign this to? 3) The design is mostly asynchronous and has one synchronous clock for a few components. When I run a post fit simulation many of the asynchronous signals do not change until I clock the one synchronous clock input signal that is not tied to any of these components of the design. I have tries un-checking the "Use Global Clocks" option with no change. Thanks in advance for any help! Edit: Right click on the image and select view image to see it full size (firefox) or save it to desktop then open it. Edit 2: The attachement below is not the full design. 0
2018-10-10 11:03:30　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答举报胡文娅相关推荐 • 关于窗口最小化的实现 5359 • 基于应用毫微功耗运算放大器实现系统功耗最小化 1185 • LabVIEW最小化的使用 5469 • 如何使FPGA设计中的功耗最小化？ 1071 • 手动最小化前面板运行内存会骤降，而程序控制最小化不行 2461 • 最小化SEPIC转换器怎么排放？ 1293 • labview最小化窗口后，会出现阴影怎么解决啊？ 4406 • vrf设置程序窗口最小化 7471 • 有没有函数能实现exe程序的最小化 3075 • 如何屏蔽labview窗口双击最大最小化? 2432 2个回答

答案对人有帮助，有参考价值 0 嗨， 1）当您将FFs D输入置于常量（此处为VCC）时，FF将被优化掉。消息是关于Reset输入发生了什么：'Status0Out.RSTF'。 2）是的，因为该工具将这些线视为时钟线。对于CPLD，这可能没问题（由于资源有限）。只需在约束文件中输入一些值（例如，与您的时钟相同。如果您有任何值）。 3）在您的原理图中，您根本没有使用PHI_CLK，存储元件只是锁存器，所以我不知道它为什么不能按预期工作。你看看芯片里面的“内部”了吗？您可以在FPGAS上使用fpga-editor用于此目的，CPLD也有类似的工具。检查宏单元内部接线方式，以便更好地了解您的设计中发生的情况。有一个很好的综合 Eilert 以上来自于谷歌翻译以下为原文 Hi, 1) When you put a FFs D-input to a constant (here VCC) the FF will be optimized away. The message is about what happened to the Reset input :'Status0Out<0>.RSTF'. 2) Yes, because the tool sees these lines as Clock lines. For CPLDs this might be OK (due to limited ressources). Just enter some value to the constraints file (e.g. the same as for your clock. if you have any). 3) In your schematic you aren't using PHI_CLK at all, and the storage elements are just latches, so I have no Idea why it shouldn't work as intended. Have you taken a look "inside" the chip? You would use fpga-editor for that purpose on FPGAS, there's a similar tool for CPLDs. Check how your Macro-Cells are internally wired up, for a better understanding of what's going on in your fitted design. Have a nice synthesis Eilert

2018-10-10 11:10:23 评论举报陈舒斌

答案对人有帮助，有参考价值 0 感谢Eilert的回复！我仍然有一些问题误解.1）哦，这是有道理的，只有当全局复位存在时，这个VCC信号才是地2）我想我并不真正理解约束编辑器。如果约束编辑器中的值对于这些异步信号来说太慢，会发生什么？设置约束比信号更快是否有害？这个工具究竟做了什么？3）第一篇文章中发布的图片并不是完整的设计。使用所有I O信号，包括PHI_CLK。在设计的其他一些元素中有D-flip翻转，这些元素在PHI_CLK和或其他一些异步信号上计时，这会改变什么吗？如何查看CPLD内部的设计布局？谢谢你的帮助！编辑：我附上了我的设计的顶部元素的副本和两个块内。它很大，所以你必须右键单击保存才能清楚地看到它。以上来自于谷歌翻译以下为原文 Thanks Eilert for the response! I still have some questions misunderstandings. 1) Oh that makes sense, only when a global reset is present this VCC signal is ground 2) I guess I do not really understand the constraints editor. What happens if the value in the constraints editor is too slow for these asynchronous signals? Does it hurt to set the constraints faster than the signal? What is this tool really doing exactly? 3) The picture posted in the first post is not the full design. All the IO signals are used including the PHI_CLK. There are D-flip flips in some other elements of the design that are clocked on the PHI_CLK ANDOR a few other asynchronous signals, does that change anything? How do I look inside the design layout inside the CPLD? Thanks for any help! Edit: I have attached a copy of the top element of my design and inside two of the blocks. It is big so you will have to right click save it to see it clearly.

2018-10-10 11:15:51 评论举报侯倩