多通道布局和路线出现错误

您可以尝试关闭Timing Driven packing＆amp;
放置，但通常是那个选项
在尝试放置和布线制作困难的大型设计时有所帮助
定时。
其他尝试：
如果你仍然有“满足时间”但也“失败”的位置，也许你可以
在FPGA编辑器中打开它。
通常只使用非结构资源的位置
像块公羊和乘法器/ DSP单元可以帮助P＆amp; R给你一个可用的
结果。
升级到较新版本的ISE。
你可以有多个版本
相同的系统，所以如果新工具有问题，你可以很容易地去 
回到8.2。
此外，如果您使用最新版本的工具，您可能会得到
当您发现错误时，来自Xiinx的更好回应。
查看后P＆amp; R时序报告，了解不符合时间的通行证
看看你是否可以通过放松一些约束来解决时间问题
改变设计。
您也可以通过合成，翻译获得帮助
和映射选项，如寄存器平衡，寄存器复制，关闭
关闭资源共享等
问候，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

You could try turning off Timing Driven packing & placement, but usually that option
helps when trying to place and route large designs that are having trouble making
timing.
 
Other things to try:
 
If you still have the placement that "met timing" but also "failed" perhaps you can
open it in FPGA editor.  Often just using the placement for non-fabric resources
like block rams and multipliers/DSP units can help P&R to give you a usable
result.
 
Upgrade to a newer version of ISE.  You can have multiple versions on the
same system, so if there are issues with the newer tools you can easily go
back to 8.2.  Also if you use the latest version of the tools you may get
better response from Xiinx when you find bugs.
 
Look through the post P&R timing report for a pass that doesn't meet timing
and see if you can fix the timing problems by relaxing some constraints or
changing the design. You may also get help by playing with synthesis, translate
and map options like register balancing, register replication, shutting
off resource sharing, etc.
 
Regards,
Gabor
-- GaborView solution in original post

作为一种解决方法，您应该能够从单次传递中获得相同的结果
如果您使用多通道P＆amp; R中的成本表条目，则放置和布线
给出了你想要的结果。
例如，如果您的起始成本表是1
（默认）和第二遍（使用表格2）完成和
遇到时间，您可以将起始成本表条目更改为2英寸
您的P＆amp; R设置和运行标准位置＆amp;
而不是路线。
问候，
的Gabor
-  Gabor



以下为原文

As a workaround, you should be able to get the same results from a single-pass
place and route if you use the cost table entry from the multipass P&R that
gave your desired results.  For example if your starting cost table was 1
(default) and the second pass (using table entry 2) completed and
met timing, you could just change the starting cost table entry to 2 in
your P&R settings and run standard place & route instead.
 
Regards,
Gabor
-- Gabor

这也是我的想法...但我尝试使用单个传递位置和路线将成本表条目设置为2并且...它不起作用。
路由与多通道的路由不同，不满足时序约束。
我很困惑。



以下为原文

that's what I thought too... but I tried with a single pass place and route setting the cost table entry to 2 and ... it didn't work.
The routing was different from what I got with multipass, timing constraint were not met.
I'm pretty confused.

我认为这个问题在8.2中已经修复，显然不是。
你可以随时做一个“手动多通道P＆amp; R”
作为解决方法，手动更改每个过程的起始成本表条目并运行
标准的P＆amp; R.
当您运行多通道P＆amp; R时，您使用的是“定时驱动包装和
放置在您的映射选项中？此选项有效地导致多次传递P＆amp; R到
只是重新进入路由，因为放置由映射器完成，而不是
在循环中重新运行。
-  Gabor



以下为原文

I thought that issue was fixed in 8.2, apparently not.  You can always do a "manual multipass P&R"
as a workaround, changing the starting cost table entry for each pass manually and running
the standard P&R.  When you ran the multipass P&R were you using "Timing driven packing and
placement" in your mapping options?  This option effectively causes multi-pass P&R to
do just re-entrant routing since the placement is done by the mapper and that is not
re-run in the loop.
-- Gabor

是的我确实使用了“定时驱动包装和放置”。
因此，如果我理解它是否可重入...... MPRR调用2的位置不是通过成本表输入2获得的位置，但它也取决于第一个位置。
那我该怎么办？
也许停用Timing驱动包装我可以测试多通道是否能够到达工作位置。
或者您建议通过手动更改起始成本表来运行多个PR。
这无论如何都很烦人......



以下为原文

Yes I did use "Timing driven packing and placement". So if I understand well if it is re-entrant ... the placement that MPRR calls 2 is not the one obtained with cost table entry to 2 but it is also dependent on the first placement.
 
So what can I do? Maybe deactivating Timing driven packing I can test if multipass is able to reach a working placement.
Or as you suggest run multiple PR by changing manually the starting cost table.
 
That's very annoying in any case ...

您可以尝试关闭Timing Driven packing＆amp;
放置，但通常是那个选项
在尝试放置和布线制作困难的大型设计时有所帮助
定时。
其他尝试：
如果你仍然有“满足时间”但也“失败”的位置，也许你可以
在FPGA编辑器中打开它。
通常只使用非结构资源的位置
像块公羊和乘法器/ DSP单元可以帮助P＆amp; R给你一个可用的
结果。
升级到较新版本的ISE。
你可以有多个版本
相同的系统，所以如果新工具有问题，你可以很容易地去 
回到8.2。
此外，如果您使用最新版本的工具，您可能会得到
当您发现错误时，来自Xiinx的更好回应。
查看后P＆amp; R时序报告，了解不符合时间的通行证
看看你是否可以通过放松一些约束来解决时间问题
改变设计。
您也可以通过合成，翻译获得帮助
和映射选项，如寄存器平衡，寄存器复制，关闭
关闭资源共享等
问候，
的Gabor
-  Gabor



以下为原文

You could try turning off Timing Driven packing & placement, but usually that option
helps when trying to place and route large designs that are having trouble making
timing.
 
Other things to try:
 
If you still have the placement that "met timing" but also "failed" perhaps you can
open it in FPGA editor.  Often just using the placement for non-fabric resources
like block rams and multipliers/DSP units can help P&R to give you a usable
result.
 
Upgrade to a newer version of ISE.  You can have multiple versions on the
same system, so if there are issues with the newer tools you can easily go
back to 8.2.  Also if you use the latest version of the tools you may get
better response from Xiinx when you find bugs.
 
Look through the post P&R timing report for a pass that doesn't meet timing
and see if you can fix the timing problems by relaxing some constraints or
changing the design. You may also get help by playing with synthesis, translate
and map options like register balancing, register replication, shutting
off resource sharing, etc.
 
Regards,
Gabor
-- Gabor

最后，我关闭了Timing Driven packing＆amp;
放置并运行Multi Pass Place＆amp;
路线。
它在第二次迭代时遇到时间限制..然后我运行一个正常位置＆amp;
路由将成本表条目设置为2，并且它有效。
无论如何，每当我改变时，我必须面对这些问题的细节时间限制，指南地图和PAR在过去有所帮助...但它并不总是按预期工作。
不幸的是，我不能放松约束，我无法更新到较新的ISE版本。
谢谢



以下为原文

Finally I turned off Timing Driven packing & placement and run Multi Pass Place & Route.
It met the timing constraint at the second iteration .. then I run a Normal Place & Route setting the Cost Table entry to 2, and it worked.
 
Anyway everytime I change also little particulars I have to face with this problems Timing Constraints, Guide Map and PAR helped a little bit in the past  ... but   it doesn't work always as expected.
Unfortunately I can't relax the constraint and I can't update to the newer ISE version.
 
Thanks