完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嗨,大家好
我有一个关于spartan-3E FAMILY INTERFACE WITH XCFxxProm的问题。 选择的模式: MAster Serial模式,M =, 问题: 假设FPGA从附加的PROM配置自己。 这真的适用于我们的项目,但有一次我们成功配置,当我们开机时10次! 主要嫌疑人: 在fpga清除其内存后,它会将CCLK发送给Prom。 然后将一个名为INIT_B的标志置为HIGH。 当配置中出现故障时,此标志会变高。 我阅读了有关CCLK引脚的设计考虑因素。 我读到我们不想从那个引脚留下长长的痕迹。 问题是: 1-长是一个实际的距离,有人知道这是多长的厘米? 2-有没有人面临同样的问题,他还有其他原因吗? 提前致谢 以上来自于谷歌翻译 以下为原文 Hi everyone I have a question about spartan-3E FAMILY INTERFACE WITH XCFxxProm. Mode selected : MAster Serial mode ,M<2:0>=<000>,Problem: It is supposed that the fpga configures itself from the attached PROM. That really works with our project, but 1 time we have successful configuration each 10 times when we power on !The main suspect : After the fpga clears its memory it sends out the CCLK to the Prom. Then a flag called INIT_B is raised HIGH. This flag nevers goes high when there is faliure in configuration. I read the design consideration about the CCLK pin. I read that we have not to make long traces out of that pin.The question: 1- Long is a realtive distance, Do anyone know howlong is that in centimeters ? 2- Did anyone face the same problem and he have another reason for that ? Thanks in advance |
|
相关推荐
1个回答
|
|
你应该仔细看看INIT_B。
如果它真的永远不会 高,然后我不会怀疑CCLK,因为这表明了 FPGA不会退出正常的上电复位状态。 但是如果 INIT_B短暂地再次变高,然后再次变低,你可能会遇到问题 CCLK。 这表示配置负载中存在CRC错误。 CCLK上的长行可能会导致振铃,而Spartan3系列则会出现振铃 当它用作输入时,该引脚易于振铃。 在你的情况下(主串行模式)CCLK是一个输出,所以信号 应在闪存芯片(XFFxxS或XCFxxP)上检查质量。 通常这些部件不易受到多次计时的影响 比Spartan3响。 如果配置失败时INIT_B线确实保持低电平,我会的 建议看看你的电源开启特性。 一个 可能的问题可能是非单调电压上升(电压变高 当斯巴达开始出现负荷时,然后下降。 如果 如果配置正确,您的系统运行良好,您可能会 能够通过添加外部来解决启动问题 上电复位电路将PROG_B驱动为低电平,直到电源为止 稳定。 HTH, 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 You should look carefully at INIT_B. If it really never goeshigh, then I would not suspect CCLK, because this indicates that theFPGA doesn't exit its normal power-on reset state. However ifINIT_B goes high briefly and then low again, you may have issues withCCLK. This would indicate a CRC error in the configuration load. Long lines on CCLK can result in ringing, and the Spartan3 series aresusceptible to ringing on this pin when it is used as an input. In your case (master serial mode) CCLK is an output, so the signalquality should be checked at the Flash chip (XFFxxS or XCFxxP). Normally these parts are less susceptible to multiple clocking due toringing than the Spartan3. If the INIT_B line really stays low when configuration fails, I wouldsuggest looking at your power-supply turn-on characteristics. Apossible problem might be non-monotonic voltage rise (the voltage goesup and then dips when the Spartan starts to present a load). Ifyour system runs well when it does configure correctly, you might beable to work around the start-up issue by adding an externalpower-on-reset circuit to drive PROG_B low until the supplies arestable. HTH, Gabor -- Gabor |
|
|
|
只有小组成员才能发言,加入小组>>
2416 浏览 7 评论
2821 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2292 浏览 9 评论
3372 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2459 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1136浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
581浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
447浏览 1评论
2002浏览 0评论
726浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-22 10:53 , Processed in 3.017461 second(s), Total 75, Slave 60 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号