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亲爱的各位,我正在和PIC16F179一起工作,我把Pi15RA1设为VREF+。事实上,我使用的是外部的2,5V电压基准。在电压基准和PN15之间,我设置了一个120欧姆的电阻。我验证了PIN寄存器的正确设置。我注意到这个电阻之间的电压下降了4MV。这意味着有一个由引脚引出的33 UA泄漏电流。也就是说,有一个和相当于输入电阻的PU15的76KOHM。在我看来,低输入电阻。你对此有何看法?这是可能还是我犯了一些错误?最好的问候,Mattia
以上来自于百度翻译 以下为原文 Dear All, I'm working with the PIC16F1769 and I've setted PIN15 RA1 as VREF+. In fact I'm using an external 2,5V voltage reference. Between Voltage reference and PIN15 I put a 120 Ohm resistor. I verified that the pin registers are setting correctly. I'm noticing a voltage drop of 4mV between this resistance. This means that there is a leakage current of 33uA drawed by the pin. Also it means that there is and an equivalent input resistance of PIN15 of 76kOhm. It seems to me a low input resistance. What do you think about this? Could it be possible or am I making some mistakes? Best Regards, Mattia |
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这些数字看起来完全合理。你为什么觉得有问题?
以上来自于百度翻译 以下为原文 Those figures seem perfectly reasonable. Why do you think there is a problem? |
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嗨,谢谢你的回答。通常ADC有MOHMS的输入电阻。我还没有在数据表上找到任何规格,所以我问它是否正确,以确保。最好的问候,马蒂亚。
以上来自于百度翻译 以下为原文 Hi, thank you for your answer. Usually ADCs have input resistance of MOhms. I haven't found any specification on the datasheet so I'm asking if it is correct in order to be sure. Best Regards, mattia |
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但是你问的是VREF+输入,而不是ADC输入,你从哪里得到的“通常兆欧”数字?所有PIC ADC输入有效地具有比这更低的阻抗,因为您必须在每个周期上对采样电容进行充电,这就是为什么它们为每个ADC输入指定小于10K的源阻抗。
以上来自于百度翻译 以下为原文 But you are asking about the Vref+ input, not an ADC input to be measured. Where did you get the "usually megaohms" figure from? All PIC ADC inputs effectively have a lower impedance than that, as you have to charge a sampling capacitor on every cycle, which is why they specify a source impedance of less than 10k for each ADC input. |
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嗨,我一直使用外部ADC,而不是微控制器ADC。谢谢你的回答,已经很清楚了。
以上来自于百度翻译 以下为原文 Hi, I've always used external ADC, not microcontrollers ADC. Thank you for your answer, it's been very clear. mattia |
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大多数高质量的ADC缓冲参考输入,因此它表现为高阻抗。我怀疑PIC VREF+输入直接应用于SAR DAC电阻梯的顶部。你看到了梯子的串联阻力。ADC的模拟输入是高阻抗(当采样盖被切换时,除了QYB指出的采样之外)。
以上来自于百度翻译 以下为原文 Most high quality ADCs buffer the reference input so it appears as high impedance. I suspect that the PIC Vref+ Input is applied directly to the top of the SAR DAC resistor ladder. You are seeing the series resistance of that ladder. Analog inputs to the ADC are high impedance (except during sampling when the sample cap is switched in as noted by qyb) |
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谢谢你的回答!我想给你打个好电话,但我犯了个错误。对不起的!
以上来自于百度翻译 以下为原文 Thank you mbrowning for your clear answer!! I wanted to rated positive you post but I made a mistake. Sorry! |
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没有问题。这是个好问题。我的答案基本上是猜测,但它是有根据的证据。有趣的是,这意味着ADCS SAR DAC电阻梯形是由7OHM电阻器(74×1024=76K)制成的。数据表不指定VREF+输入电流,但IO为5Na TYP。
以上来自于百度翻译 以下为原文 no prob. was a good question. My answer is essentially speculation, but it makes sense based on the evidence. Interestingly, this would mean that the ADCs SAR DAC resistor ladder is made of 74ohm resistors (74*1024 = 76K). The datasheet doesn't spec Vref+ input current, but IO are 5nA typ. |
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