请教关于6678 bootloader DDR参数表的问题

不能通过DDR3 Boot Parameter Table 配置DDR3
如果你是通过PCIE,SRIO接口启动，通过它们可以直接读写DDR配置寄存器。
如果通过其它不能直接访问DDR寄存器的接口加载，那就只有分步来做了：
1，加载部分程序到片内Memory
2，运行片内程序，用片内运行的程序初始化DDR
3，加载程序到DDR

hi，您好
我在用6678 evm测试的时候，所有的程序段分配在DDR，传入以下DDR参数表
00 00 00 70 00 87 35 00 02 42 80 F5 00 00 00 00 00 00 00 1C 00 00 00 02
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 03 05
是可以正常boot 的，我的理解是这些参数对DDR做了初始化才使得boot 能够成功，不知对不对？
谢谢！

请问你用的什么加载方式？你用的配置值是怎么得出来的？

您好，
我用的是SPI加载，根据tiboot.h下的DDR配置参数结构体：
typedef struct bootEmif4Tbl_s [
UINT32 configSelect; /* Bit map defining which registers to set */

UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;
UINT32 sdRamConfig;
UINT32 sdRamConfig2;
UINT32 sdRamRefreshCtl;
UINT32 sdRamTiming1;
UINT32 sdRamTiming2;
UINT32 sdRamTiming3;
UINT32 lpDdrNvmTiming;
UINT32 powerManageCtl;
UINT32 iODFTTestLogic;
UINT32 performCountCfg;
UINT32 performCountMstRegSel;
UINT32 readIdleCtl;
UINT32 sysVbusmIntEnSet;
UINT32 sdRamOutImpdedCalCfg;
UINT32 tempAlterCfg;
UINT32 ddrPhyCtl1;
UINT32 ddrPhyCtl2;
UINT32 priClassSvceMap;
UINT32 mstId2ClsSvce1Map;
UINT32 mstId2ClsSvce2Map;
UINT32 eccCtl;
UINT32 eccRange1;
UINT32 eccRange2;
UINT32 rdWrtExcThresh;

] BOOT_EMIF4_TBL_T;
然后传入对应DDR初始化需要的值，但是没发现与leveling的操作相关的配置
谢谢！

Leveling寄存器没有配置时会用缺省值，这对某些板子可能可以，但绝对不是一个可靠的配置。
如果你用SPI加载的话，可以试以下bootloader user's guide中介绍的方法:
3.2.3 Boot Configuration Table
A boot configuration table is used if certain peripherals must be programmed with
values that differ from their reset values before loading an application. For example, if
the application needs to be loaded into DDR memory, the boot configuration table can
be used to program the DDR registers and enable the DDR peripheral before loading
the application code into DDR.
Each table entry in the boot configuration table has three elements:
• The address to be modified
• The set mask
• The clear mask
The RBL reads the specified address, then sets any bits that are set in the set mask
element and clears any bits that are set in the clear mask element. If both the set and
clear mask elements are 0, the value in the address field is branched via a standard call
with the return address stored in register B3. The boot configuration table is terminated
when all three elements are 0.

你好，我的DDR型号和EVM有些差别，请问如何产生DDR配置参数，还有开始的UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;UINT32 pllPostDiv;这几个值怎么确定，有什么手册吗？

你说的几个参数是用来配置DDR PLL的，PLLOUT=input_CLK*(PLLM+1)/PLLD,在C6678 data manual中有
其他的DDR参数使用如下链接的spreadsheet生成：
http://www.deyisupport.com/question_answer/dsp_arm/c6000_multicore/f/53/t/53384.aspx