omapl138的ARM端linux操作系统下能操作uPP接口么？

问题已解决，依然是ARM端控制UPP

        我近期也在linux操作系统下编写upp驱动，能够触发upp接收中断，但接收到的数据全部是零，回环测试也是失败，能提供upp驱动源码供学习参考，谢谢。以下是我的初始化代码：
typedef struct UPP_REG_STRUCT{
    UINT32 ID_U32;    /*UPP ID 寄存器*/
    UINT32 Ctrl_U32;/*UPP Control 寄存器*/
    UINT32 DLB_U32;/*UPP Digital LoopBack 寄存器*/
    UINT32 Reserved5_U32;/*Reserved*/
    UINT32 CHCtrl_U32;/*UPP Channal Control 寄存器*/
    UINT32 ICfg_U32;/*Interface Configuration 寄存器*/
    UINT32 IVR_U32;/*Interface Idle Value 寄存器*/
    UINT32 ThCfg_U32;/*Threshold Configuration  寄存器*/
    UINT32 IntStat_U32;/*Interrupt Status 寄存器*/
    UINT32 IntEnStat_U32;/*Interrupt Enabled Status  寄存器*/
    UINT32 IntEnSet_U32;/*Interrupt Enabled Set  寄存器*/
    UINT32 IntEnClr_U32;/*Interrupt Enabled Clear 寄存器*/
    UINT32 EndofInt_U32;/*End-of-Interrupt 寄存器*/
    UINT32 Reserved_aU32[3];/*Reserved*/
    UINT32 DMACHNID0_U32;/*DMA Channel I Descriptor 0 寄存器*/
    UINT32 DMACHNID1_U32;/*DMA Channel I Descriptor 1 寄存器*/
    UINT32 DMACHNID2_U32;/*DMA Channel I Descriptor 2 寄存器*/
    UINT32 Reserved1_U32;/*Reserved*/
    UINT32 DMACHNIS0_U32;/*DMA Channel I Status 0 寄存器*/
    UINT32 DMACHNIS1_U32;/*DMA Channel I Status 1 寄存器*/
    UINT32 DMACHNIS2_U32;/*DMA Channel I Status 2 寄存器*/
    UINT32 Reserved2_U32;/*Reserved*/
    UINT32 DMACHNQD0_U32;/*DMA Channel Q Descriptor 0 寄存器*/
    UINT32 DMACHNQD1_U32;/*DMA Channel Q Descriptor 1 寄存器*/
    UINT32 DMACHNQD2_U32;/*DMA Channel Q Descriptor 2 寄存器*/
    UINT32 Reserved3_U32;/*Reserved*/
    UINT32 DMACHNQS0_U32;/*DMA Channel Q Status 0 寄存器*/
    UINT32 DMACHNQS1_U32;/*DMA Channel Q Status 1 寄存器*/
    UINT32 DMACHNQS2_U32;/*DMA Channel Q Status 2 寄存器*/
}UPP_REG;

static int __init omapl138_upp_init(VOID)
{
    volatile unsigned long *p_Temp = NULL;
    UINT32 Delay_U32 = 2000U;

    printk("Load upp module function!n");
    printk("Current Version is V%d.0n",UPP_VERSION);
    printk("Author:Ben Date:2019-04-01n");
   
    //register_chrdev(GPIO_LED_MAJOR,"omapl138gpio",&leds_drv_file_operation);
    major = register_chrdev(0,"omapl138upp",&upp_drv_file_operation);/*Alloc Major Num auto*/
   
    io_mem = request_region(SOC_SYSCFG_0_REGS, 0x100, "io");
    if (io_mem == NULL)
    {
      printk("failed to get memory regionn");
    }


    /*Set upp gpio mux*/
    p_Temp = ioremap(SOC_SYSCFG_0_REGS, 0x100);
    if(NULL == p_Temp)
    {   
        release_resource(io_mem);
        kfree(io_mem);
        printk("ioremap1 failn");
        return -1;
    }
   
    *(p_Temp + 13) &= 0x0000FFFF;
    *(p_Temp + 13) |= 0x44440000;/*GPIO6[8]~GPIO6[11]*/

    *(p_Temp + 14) &= 0x000000FF;
    *(p_Temp + 14) |= 0x44444400;/*UPP_D10~UPP_D15*/

    *(p_Temp + 15) = 0x44444444;
    *(p_Temp + 16) = 0x44444444;
    *(p_Temp + 17) = 0x44444444;

    *(p_Temp + 18) &= 0xFF000000;
    *(p_Temp + 18) |= 0x00444444;
    iounmap(p_Temp);

    /* 使能upp时钟 */
    //davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, 1,
    //                19, 1);
    /* 映射io寄存器 */
    p_Reg =  ioremap(UPP_BASE_REGS, 0x100);
    if(NULL == p_Reg)
    {   
        printk("ioremap2 failn");
        return -1;
    }   

    p_Reg->Ctrl_U32 &= ~UPP_UPPCR_EN;
    while((p_Reg->Ctrl_U32 & UPP_UPPCR_DB) != 0U)
    {
    }
    p_Reg->Ctrl_U32 |= UPP_UPPCR_SWRST;

    while(Delay_U32 > 0U)
    {
        Delay_U32 --;
    }

    p_Reg->Ctrl_U32 &= ~UPP_UPPCR_SWRST;
    p_Reg->Ctrl_U32 |= UPP_UPPCR_SOFT | UPP_UPPCR_RTEMU;

    p_Reg->CHCtrl_U32 = 0x02020007U;
    p_Reg->DLB_U32 &= ~0x1000U;
    //p_Reg->DLB_U32 |= 0x1000U;
    p_Reg->ICfg_U32 = 0x00180F18U;
    p_Reg->IVR_U32 = 0x00000000U;
    p_Reg->ThCfg_U32 = 0x000000U;
    p_Reg->IntEnClr_U32 = 0x0001F1FU;
    p_Reg->IntEnSet_U32 = 0x0001000U;   
    p_Reg->Ctrl_U32 |= UPP_UPPCR_EN;

    bsp_upp_InitRecv();

    upp_class = class_create(THIS_MODULE,"upp class");
    if(!upp_class)
    {
         if(IS_ERR(upp_class))
         {
            return PTR_ERR(upp_class);
         }
    }   

    upp_dev = device_create(upp_class,NULL,MKDEV(major,0),NULL,"upp");
    if(!upp_dev)
    {
         if(IS_ERR(upp_dev))
         {
            return PTR_ERR(upp_dev);
         }
    }

    return 0;