之前做了一个CPLD+SRAM的方案 ， 但是屏幕上总是跳乱点。哪位能帮忙分析一下

`硬件电路检测了也没有找到问题的原因在哪儿  ，哪位能帮忙分析一下原因呢？  估计应该是SRAM的问题 这里附上SRAM的代码 请各位帮忙分析一下。

//-----------------------------------------------
//SRAM address switch. User's SRAM operate have higher priority then display SRAM operate.
//User write SRAM when regaddr=2 and read SRAM no need regaddr.
//-----------------------------------------------
always @ (posedge sys_clk, negedge reset) begin
    if (!reset)
                addr <= `TD 18'd0;
        else if ((nwr_state == 2'b01 && ncs_state[1] == 1'd0 && dnc_state[1] == 1'd1 && regaddr == 2'd2) || (nrd_state == 2'b10 && ncs_state[0] == 1'd0 && dnc_state[1] == 1'd1)) begin
                addr[17] <= `TD reg_set[2];
                addr[16:0] <= `TD reg_x + reg_y * 9'd320;
        end
        else if (clear_flag != 2'd0 && clkcount == 3'd3)
                addr <= `TD {reg_set[2], dispaddr};
    else if (clkcount == 3'd1 || clkcount == 3'd2)
        addr <= `TD {reg_set[3], dispaddr};
end

//-----------------------------------------------
//Read display color data form SRAM
//-----------------------------------------------
always @ (posedge sys_clk, negedge reset) begin
    if (!reset)
        rgb <= `TD 16'd0;
    else if (we != 1'd0 && nrd_flag != 1'd1 && (clkcount == 3'd2 || clkcount == 3'd3))
        rgb <= `TD io;
end

//-----------------------------------------------
//Write SRAM control.
//-----------------------------------------------
always @ (posedge sys_clk, negedge reset) begin
    if (!reset)
                we <= `TD 1'd1;
    else if (nwr_state == 2'b01 && ncs_state[1] == 1'd0 && dnc_state[1] == 1'd1 && regaddr == 2'd2)
        we <= `TD 1'd0;
    else if (clear_flag != 2'd0 && clkcount == 3'd3)
        we <= `TD 1'd0;
    else
            we <= `TD 1'd1;
end

//-----------------------------------------------
//It's a SRAM read flag, like we.
//-----------------------------------------------
always @ (posedge sys_clk, negedge reset) begin
    if (!reset)
                nrd_flag <= `TD 1'd0;
    else if (nrd_state == 2'b10 && ncs_state[0] == 1'd0 && dnc_state[1] == 1'd1)
        nrd_flag <= `TD 1'd1;
    else
            nrd_flag <= `TD 1'd0;
end


//-----------------------------------------------
//Read SRAM control
//-----------------------------------------------
always @ (posedge sys_clk, negedge reset) begin
    if (!reset)
        reg_ram <= `TD 16'd0;
    else if (nrd_flag == 1'd1)
        reg_ram <= `TD io;
    else if (nwr_state == 2'b01 && ncs_state[1] == 1'd0 && dnc_state[1] == 1'd1 && regaddr == 3'd4)
            reg_ram <= `TD db_state[15:0];
end

`

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