[资料]

Validating and Debugging DDR2, DDR3 SDRAM Designs

2010-6-29 17:27:32 2514

0 Memory Design and Validation Chip/Component Design -Precise understanding of circuit behavior under range of conditions -Margin testing System Integration -Signal integrity and timing analysis, discovery of issues under nominal conditions -Debug interoperability issues Embedded Systems -Easy test setup -Quick pass/fail results DDR Test Challenges -Signal Access & Probing – Easy-to-use / reliable connections – Bandwidth & Signal Integrity – Affordable -Isolation of Read/Write bursts – Triggering or Post-Processing -Complexity of JEDEC Conformance Tests – Parametric timing/amplitude measurements – Vref / Vih / Vil, Derating -Results Validity / Statistics -Effective Reporting / Archiving -Advanced Analysis – Characterization – Debug BsxSy75B.rar (844.85 KB, 下载次数: 7 ) EIMLqUpt.rar (1.52 MB, 下载次数: 9 ) 0
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