[资料]

Validating and Debugging DDR2, DDR3 SDRAM Designs

2010-6-29 17:27:32 2530

0 Memory Design and Validation Chip/Component Design -Precise understanding of circuit behavior under range of conditions -Margin testing System Integration -Signal integrity and timing analysis, discovery of issues under nominal conditions -Debug interoperability issues Embedded Systems -Easy test setup -Quick pass/fail results DDR Test Challenges -Signal Access & Probing – Easy-to-use / reliable connections – Bandwidth & Signal Integrity – Affordable -Isolation of Read/Write bursts – Triggering or Post-Processing -Complexity of JEDEC Conformance Tests – Parametric timing/amplitude measurements – Vref / Vih / Vil, Derating -Results Validity / Statistics -Effective Reporting / Archiving -Advanced Analysis – Characterization – Debug BsxSy75B.rar (844.85 KB, 下载次数: 7 ) EIMLqUpt.rar (1.52 MB, 下载次数: 9 ) 0
举报淘帖0 只看该作者最近下载过的用户(1) 相关推荐 • DR2与DDR有哪些区别？DDR3与DDR2的区别是什么？ 2132 • 浅析DDR,DDR2,DDR3,DDR4,LPDDR区别 1657 • DDR4,DDR3,DDR2,DDR1及SDRAM有什么不同之处? 2619 • 怎么将DDR2 SDRAM连接到Virtex-4QV FPGA？ 1351 • 如何使用DDR2 SDRAM？ 1426 • DDR2 DDR3 dimm接口封装文件 JETEC标准封装 9026 • 详解：SDR/DDR/DDR2/SDRAM的功能及异同 14454 • 【小知识分享】SDR/DDR1/DDR2/DDR3的接口区别 5104 • 【小知识分享】SDR/DDR1/DDR2/DDR3的接口区别 3015 • 你知道DDR2和DDR3的区别吗？ 8440