module at93c46_mix(
clk ,
rst_n ,
start ,
mode ,
addr ,
wdata ,
rdata ,
rdata_vld ,
rdy ,
do ,
di ,
cs ,
sk
);
parameter DATA_W = 8 ;
parameter EWEN = 2'b00 ;
parameter WRITE = 2'b01 ;
parameter READ = 2'b10 ;
input clk ;
input rst_n ;
input [6:0] addr ;
input [1:0] mode ;
input start ;
input do ;
input [DATA_W-1:0] wdata ;
output rdy ;
output di ;
output cs ;
output sk ;
output[DATA_W-1:0] rdata ;
output rdata_vld ;
reg [DATA_W-1:0] rdata ;
reg rdata_vld ;
reg rdy ;
reg di ;
reg cs ;
reg sk ;
reg [17:0] data ;
reg [1:0] flag ;
reg [16:0] cnt0 ;
reg [4:0] cnt1 ;
reg cnt2 ;
reg [16:0] x ;
reg [4:0] y ;
reg [1:0] m ;
reg [1:0] work_flag ;
wire add_cnt0 ;
wire end_cnt0 ;
wire add_cnt1 ;
wire end_cnt1 ;
wire add_cnt2 ;
wire end_cnt2 ;
wire mid_cnt0 ;
wire fir_cnt0 ;
always @(posedgeclk or negedgerst_n)begin
if(!rst_n)begin
cnt0 <= 0;
end
else if(add_cnt0)begin
if(end_cnt0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
end
end
assign add_cnt0 = work_flag;
assign end_cnt0 = add_cnt0 && cnt0==x-1 ;
always @(posedgeclk or negedgerst_n)begin
if(!rst_n)begin
cnt1 <= 0;
end
else if(add_cnt1)begin
if(end_cnt1)
cnt1 <= 0;
else
cnt1 <= cnt1 + 1;
end
end
assign add_cnt1 = end_cnt0;
assign end_cnt1 = add_cnt1 && cnt1==y-1 ;
always @(posedgeclk or negedgerst_n)begin
if(!rst_n)begin
cnt2 <= 0;
end
else if(add_cnt2)begin
if(end_cnt2)
cnt2 <= 0;
else
cnt2 <= cnt2 + 1;
end
end
assign add_cnt2 = end_cnt1;
assign end_cnt2 = add_cnt2 && cnt2==m-1 ;
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
flag <= 0;
end
else if(start && mode==EWEN)begin
flag <= 0;
end
else if(start && mode==WRITE)begin
flag <= 1;
end
else if(start && mode==READ)begin
flag <= 2;
end
end
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
data <= 0;
end
else if(start && mode==EWEN)begin
data <= {3'b100,addr,wdata};
end
else if(start && mode==WRITE)begin
data <= {3'b101,addr,wdata};
end
else if(start && mode==READ)begin
data <= {3'b110,addr,wdata};
end
end
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
work_flag<= 0;
end
else if(start)begin
work_flag<= 1;
end
else if(end_cnt2)begin
work_flag<= 0;
end
end
assign mid_cnt0 = add_cnt0 && cnt0==50-1 && cnt2==1-1;
assign fir_cnt0 = add_cnt0 && cnt0== 1-1 && cnt2==1-1;
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
sk<= 0;
end
else if(mid_cnt0) begin
sk<= 1;
end
else if(end_cnt0) begin
sk<= 0;
end
end
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
di <= 1'b0;
end
else if(fir_cnt0)begin
di <= data[17-cnt1];
end
end
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
cs<= 1'b0;
end
else if(mode==WRITE || (end_cnt1 && cnt2==2-1 && flag==1))begin
cs<= 1'b1;
end
else if(end_cnt1 && (cnt2==1-1 || cnt2==3-1))begin
cs<= 1'b0;
end
end
always @(*)begin
if(mode==WRITE || work_flag)
rdy = 1'b0;
else
rdy = 1'b1;
end
always @(*)begin
if(cnt2==1-1 && flag==0)begin
x = 100;
y = 10;
end
else if(cnt2==1-1 && (flag==2-1 || flag==3-1))begin
x = 100;
y = 18;
end
else if(cnt2==2-1)begin
x = 100;
y = 1;
end
else begin
x = 100000;
y = 1 ;
end
end
always @(*)begin
if(flag==1)begin
z = 3;
else
z = 2;
end
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
rdata<= 0;
end
else if(end_cnt0 && cnt1 >= 11 && flag==2) begin
rdata<= {rdata[6:0],do};
end
end
always @(posedgeclk or negedgerst_n)begin
if(rst_n==1'b0)begin
rdata_vld<= 1'b0;
end
else if(end_cnt2 && flag==2) begin
rdata_vld<= 1'b1;
end
else begin
rdata_vld<= 1'b0;
end
end
endmodule
0
/7 
工商网监
湘ICP备2023018690号
4302
淘帖
1461
发表评论
赞
回复
