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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENtiTY traffic_control IS PORT( clk :IN STD_LOGIC; c1,c2,c3:OUT STD_LOGIC; w1,w2,w3:IN STD_LOGIC; r1,r2 :OUT STD_LOGIC; y1,y2 :OUT STD_LOGIC; g1,g2 :OUT STD_LOGIC; reset :IN STD_LOGIC); END traffic_control; ARCHITECTURE a OF traffic_control IS TYPE STATE_SPACE IS(S0,S1,S2,S3); SIGNAL state:STATE_SPACE; BEGIN PROCESS(clk) BEGIN IF reset='1' THEN state<= S0; ELSIF(clk'EVENT AND clk='1') THEN CASE state IS WHEN S0=> IF w1='1' THEN state<=S1; END IF; WHEN S1=> IF w2='1' THEN state<=S2; END IF; WHEN S2=> IF w3='1' THEN state<=S3; END IF; WHEN S3=> IF w2='1' THEN state<=S0; END IF; END CASE; END IF; END PROCESS; c1<='1' WHEN state=S0 ELSE '0'; c2<='1' WHEN state=S1 OR state=S3 ELSE '0'; c3<='1' WHEN state=S2 ELSE '0'; r1<='1' WHEN state=S1 OR state=S0 ELSE '0'; y1<='1' WHEN state=S3 ELSE '0'; g1<='1' WHEN state=S2 ELSE '0'; r2<='1' WHEN state=S2 OR state=S3 ELSE '0'; y2<='1' WHEN state=S1 ELSE '0'; g2<='1' WHEN state=S0 ELSE '0'; END a; Error (10500): VHDL syntax error at traffic_control.vhd(15) near text "SIGNALÂ"; expecting "begin", or a declaration statement Error (10500): VHDL syntax error at traffic_control.vhd(17) near text "Â"; expecting "begin", or a declaration statement Error: Quartus II 64-Bit Create Symbol File was unsuccessful. 2 errors, 0 warnings |
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