用verilog怎么实现取一组数中绝对值最大的数

做的小波滤波器  滤波完后需要这样的一个算法：s=s/max(abs(s));
s为滤完波的一组数 有10000个点，abs取绝对值  max取最大
下面是我写的代码  但是总报错：
module mas( a,res,clk,rst_n);
        input clk,rst_n;
        input signed[31:0]a;
        output signed[30:0] res;
        wire[30:0]result;
        wire[30:0] X[9999:0];
        genvar i;
        generate
        for(i=1;i==10000;i=i+1) begin:abs00
                mas0        u0 (.clk  (clk),.rst_n (rst_n),.a (a),.result (result));
        assign X[10000-i] = result;
        end
        endgenerate
        reg signed[30:0] max;
        always@(posedge clk) max <= X[N];
        genvar N;
        generate
   for(N=10000;N==0;N=N-1) begin:ma
        if(max < X[N-1])  
         max <= X[N-1];
        end
        endgenerate
endmodule



Error (10170): Verilog HDL syntax error at mas.v(34) near text "<=";  expecting ".", or "("
Error (10112): Ignored design unit "mas" at mas.v(1) due to previous errors
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
        Error: Peak virtual memory: 450 megabytes
        Error: Processing ended: Mon Dec 05 11:03:08 2016
        Error: Elapsed time: 00:00:00
        Error: Total CPU time (on all processors): 00:00:00
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning