VHDL 语言问题 在process里面 1 if语句块和2 case语句块两个我换下位置 结果不一样

architecture Behavioral of nx3_top is
type state_type is (S0,S1,S2,S3);
signal state: state_type;
begin

process(clk)

        begin
            
        if(rising_edge(clk)) then
         if state=S0 then                           --1
          leds(0)<='0';leds(1)<='0';leds(2)<='1';leds(3)<='0';
          end if;

        case state is                              --2
      when S0=> if buttons='1' and switches(0)='0' and switches(1)='0' and       switches(2)='0' and switches(3)='0' then leds(0) <='1'; state<=S1;end if;
      when S1=> if buttons='1'  and switches(0)='0' and switches(1)='1' and s  w  itches(2)='1' and switches(3)='0' then leds(1) <='1';state<=S2;end if;
      when S2=> if buttons='1'  and switches(0)='1' and switches(1)='0' and switches(2)='0' and switches(3)='0' then leds(2) <='1';state<=S3; end if;
      when S3=> if buttons='1'  and switches(0)='1' and switches(1)='0' and switches(2)='1' and switches(3)='0' then leds(3) <='1';state<=S0; end if;
      when others=> state<=S0;
     end case;
                       
end if;
end process;

先写1 if语句块在写case语句块是对的 反一下就不对了 但是我感觉没什么关系啊

end Behavioral