quartus 2和modlesim的联合仿真

是不是你取得名字刚好是VHDL中的关键字了，你改一下，如ads_8bit

改了，之后就是这样
# Reading D:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl
# do abs_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
#         vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:altera13.0sp1modelsim_asewin32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:altera13.0sp1modelsim_asewin32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
#
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/write_command_reply_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity write_command_reply_module
# -- Compiling architecture write_command_reply_module_arc of write_command_reply_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/undefine_command_reply_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity undefine_command_reply_module
# -- Compiling architecture undefine_command_reply_module_arc of undefine_command_reply_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/slave_process_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity slave_process_module
# -- Compiling architecture slave_process_module_arc of slave_process_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/sampleclk.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity sampleclk
# -- Compiling architecture behav of sampleclk
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/read_write_command_reply_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity read_write_command_reply_module
# -- Compiling architecture read_write_command_reply_module_arc of read_write_command_reply_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/read_command_reply_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity read_command_reply_module
# -- Compiling architecture read_command_reply_module_arc of read_command_reply_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/lsor6.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity lsor6
# -- Compiling architecture lsor6_arc of lsor6
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/lsor3.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity lsor3
# -- Compiling architecture lsor3_arc of lsor3
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/lsor2.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity lsor2
# -- Compiling architecture lsor2_arc of lsor2
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/high_priority_supervisor.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity high_priority_supervisor
# -- Compiling architecture BEHAIVER of high_priority_supervisor
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/gpmc_tri_buf.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity gpmc_tri_buf
# -- Compiling architecture behav of gpmc_tri_buf
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/framing_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity framing_module
# -- Compiling architecture framing_module_arc of framing_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/fram_send_module1.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity fram_send_module1
# -- Compiling architecture fram_send_module1_arc of fram_send_module1
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/fram_recive_watchdog.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity fram_recive_watchdog
# -- Compiling architecture BEHAIVER of fram_recive_watchdog
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/fram_recive.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity fram_recive
# -- Compiling architecture fram_recive_arc of fram_recive
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/fram_analysis.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity fram_analysis
# -- Compiling architecture BEHAIVER of fram_analysis
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/error_process_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity error_process_module
# -- Compiling architecture error_process_module_arc of error_process_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/device_scan_command_reply_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity device_scan_command_reply_module
# -- Compiling architecture device_scan_command_reply_module_arc of device_scan_command_reply_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/byte_send.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity byte_send
# -- Compiling architecture byte_send_arc of byte_send
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/byte_recive.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity byte_recive
# -- Compiling architecture byte_recive_arc of byte_recive
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/baud_gen.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity baud_gen
# -- Compiling architecture BEHAIVER of baud_gen
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/altdpram5.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity altdpram5
# -- Compiling architecture SYN of altdpram5
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/altdpram0.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity altdpram0
# -- Compiling architecture SYN of altdpram0
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/Tamagawa_ABS_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity Tamagawa_ABS_module
# -- Compiling architecture behav of Tamagawa_ABS_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/latchdata.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity latchdata
# -- Compiling architecture behav of latchdata
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/input_data_module.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity input_data_module
# -- Compiling architecture Behavioral of input_data_module
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/reset_gen.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity reset_gen
# -- Compiling architecture behav of reset_gen
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/lpm_constant0.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity lpm_constant0
# -- Compiling architecture SYN of lpm_constant0
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/lpm_constant1.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity lpm_constant1
# -- Compiling architecture SYN of lpm_constant1
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/altpll0.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity altpll0
# -- Compiling architecture SYN of altpll0
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/ABS_config.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity ABS_config
# -- Compiling architecture behav of ABS_config
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/lpm_constant4.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity lpm_constant4
# -- Compiling architecture SYN of lpm_constant4
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/LPM_CONSTAN22.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity LPM_CONSTAN22
# -- Compiling architecture SYN of lpm_constan22
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/input_data_module1.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity input_data_module1
# -- Compiling architecture Behavioral of input_data_module1
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/output_files/lpm_constant0001.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity lpm_constant0001
# -- Compiling architecture SYN of lpm_constant0001
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/output_files/lpm_constant0002.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity lpm_constant0002
# -- Compiling architecture SYN of lpm_constant0002
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/mode_change.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity mode_change
# -- Compiling architecture behav of mode_change
#
# vcom -93 -work work {C:/Users/zjg/Desktop/FPGA/simulation/modelsim/abs.vht}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity abs_vhd_tst
# -- Compiling architecture abs_arch of abs_vhd_tst
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneii -L rtl_work -L work -voptargs="+acc"  abs
# vsim -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneii -L rtl_work -L work -voptargs="+acc" -t 1ps abs
# ** Error: (vsim-3170) Could not find 'C:/Users/zjg/Desktop/FPGA/simulation/modelsim/rtl_work.abs'.
#
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./abs_run_msim_rtl_vhdl.do PAUSED at line 48
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line
# A time value could not be extracted from the current line

后面的错误是为什么

好吧，解决了