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手头有个JZ2440,尝试把ucosii移植到开发板上,在网上找了些相关代码进行移植,编译器使用keil 5 ,遇到启动代码不能跳转到main函数;
1、在启动代码中加入了几个点灯的动作观察代码运行的位置,可以看到启动汇编文件,可以运行到bl main这句指令之前,就不能往下走了,看灯的现象好像是汇编代码移植在重启,请求帮忙解答,谢谢! 2、keil 5 编译出来的ucosii.bin文件使用u-boot烧写到开发板的nand flash中,但是ucosii.bin文件是大于0x40000的,烧写时有如下提示,不知是否烧写成功; Now, Downloading [ADDRESS:30000000h,TOTAL:315662] RECEIVED FILE SIZE: 315662 (308KB/S, 1S) NAND erase: device 0 offset 0x0, size 0x40000 Erasing at 0x20000 -- 100% complete. OK NAND write: device 0 offset 0x0, size 0x40000 Writing data at 0x3f800 -- 100% complete. 262144 bytes written: OK(其中262144转换成十六进制刚好是0x40000); 3、以下是我的启动代码和keil软件的一些设置,求大侠帮忙解答,谢谢。 [Asm] 纯文本查看 复制代码 ;=========================================; NAME: 2440INIT.S; DESC: C start up codes; Configure memory, ISR ,stacks;Initialize C-variables; HISTORY:; 2002.02.25:kwtark: ver 0.0; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode; 2003.03.14:DonGo: Modified for 2440.;=========================================GET option.incGET memcfg.incGET 2440addr.incBIT_SELFREFRESH EQU(1<<22);Pre-defined constantsUSERMODE EQU 0x10FIQMODE EQU 0x11IRQMODE EQU 0x12SVCMODE EQU 0x13ABORTMODE EQU 0x17UNDEFMODE EQU 0x1bMODEMASK EQU 0x1fNOINT EQU 0xc0;The location of stacksUserStackEQU(_STACK_BASEADDRESS-0x3800);0x33ff4800 ~SVCStackEQU(_STACK_BASEADDRESS-0x2800);0x33ff5800 ~UndefStackEQU(_STACK_BASEADDRESS-0x2400);0x33ff5c00 ~AbortStackEQU(_STACK_BASEADDRESS-0x2000);0x33ff6000 ~IRQStackEQU(_STACK_BASEADDRESS-0x1000);0x33ff7000 ~FIQStackEQU(_STACK_BASEADDRESS-0x0);0x33ff8000 ~; :::::::::::::::::::::::::::::::::::::::::::::; BEGIN: Power Management ; - - - - - - - - - - - - - - - - - - - - - - -Mode_USR EQU 0x10Mode_FIQ EQU 0x11Mode_IRQ EQU 0x12Mode_SVC EQU 0x13Mode_ABT EQU 0x17Mode_UND EQU 0x1BMode_SYS EQU 0x1FI_Bit EQU 0x80F_Bit EQU 0x40; - - - - - - - - - - - - - - - - - - - - - - -;Check if tasm.exe(ARMasm -16 ...@ADS 1.0) is used.GBLL THUMBCODE[ {CONFIG} = 16THUMBCODE SETL {TRUE} CODE32 |THUMBCODE SETL {FALSE} ] MACROMOV_PC_LR [ THUMBCODE bx lr | movpc,lr ]MEND MACROMOVEQ_PC_LR [ THUMBCODE bxeq lr | moveq pc,lr ]MEND MACRO$HandlerLabel HANDLER $HandleLabel$HandlerLabelsubsp,sp,#4;decrement sp(to store jump address)stmfdsp!,{r0};PUSH the work register to stack(lr does''t push because it return to original address)ldr r0,=$HandleLabel;load the address of HandleXXX to r0ldr r0,[r0] ;load the contents(service routine start address) of HandleXXXstr r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stackldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)MENDIMPORT |Image$$ER_ROM1$$Base|; Base of ROM codeIMPORT |Image$$ER_ROM1$$Limit| ; End of ROM code (=start of ROM data)IMPORT |Image$$RW_RAM1$$Base| ; Base of RAM to initialiseIMPORT |Image$$RW_RAM1$$Base| ; Base and limit of areaIMPORT |Image$$RW_RAM1$$Limit| ; to zero initialise;IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data);IMPORT |Image$$RW$$Base| ; Base of RAM to initialise;IMPORT |Image$$ZI$$Base| ; Base and limit of area;IMPORT |Image$$ZI$$Limit| ; to zero initialiseIMPORTMMU_SetAsyncBusModeIMPORTCopyProgramFromNandIMPORT OS_CPU_IRQ_ISR ;uCOS_II IrqISREXPORT ResetHandler ;ìí¼ó′úÂ루2016.9.1-23£o31£©EXPORT HandleEINT0 ;for os_cpu_a.sPRESERVE8 ;DT¸Ä£¨2016.8.27-1:27£©AREA RESET,CODE,READONLY ;ENTRYEXPORT __ENTRY__ENTRYResetEntry;1)The code, which converts to Big-endian, should be in little endian code.;2)The following little endian code will be compiled in Big-Endian mode.; The code byte order should be changed as the memory bus width.;3)The pseudo instruction,DCD can not be used here because the linker generates error.ASSERT:DEF:ENDIAN_CHANGE[ ENDIAN_CHANGE ASSERT :DEF:ENTRY_BUS_WIDTH [ ENTRY_BUS_WIDTH=32bChangeBigEndian ;DCD 0xea000007 ] [ ENTRY_BUS_WIDTH=16andeqr14,r7,r0,lsl #20 ;DCD 0x0007ea00 ] [ ENTRY_BUS_WIDTH=8streqr0,[r0,-r10,ror #1] ;DCD 0x070000ea ]| bResetHandler ]bHandlerUndef;handler for Undefined modebHandlerSWI ;handler for SWI interruptbHandlerPabort;handler for PAbortbHandlerDabort;handler for DAbortb. ;reservedbHandlerIRQ;handler for IRQ interruptbHandlerFIQ;handler for FIQ interrupt;@0x20bEnterPWDN; Must be @0x20.ChangeBigEndian;@0x24[ ENTRY_BUS_WIDTH=32 DCD0xee110f10;0xee110f10 => mrc p15,0,r0,c1,c0,0 DCD0xe3800080;0xe3800080 => orr r0,r0,#0x80; //Big-endian DCD0xee010f10;0xee010f10 => mcr p15,0,r0,c1,c0,0][ ENTRY_BUS_WIDTH=16 DCD 0x0f10ee11 DCD 0x0080e380 DCD 0x0f10ee01][ ENTRY_BUS_WIDTH=8 DCD 0x100f11ee DCD 0x800080e3 DCD 0x100f01ee ]DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.DCD 0xffffffffDCD 0xffffffffDCD 0xffffffffDCD 0xffffffffb ResetHandler;Function for entering power down mode; 1. SDRAM should be in self-refresh mode.; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.; 4. The I-cache may have to be turned on.; 5. The location of the following code may have not to be changed.;void EnterPWDN(int CLKCON);EnterPWDNmov r2,r0;r2=rCLKCONtst r0,#0x8;SLEEP mode?bne ENTER_SLEEPENTER_STOPldr r0,=REFRESHldr r3,[r0];r3=rREFRESHmov r1, r3orr r1, r1, #BIT_SELFREFRESHstr r1, [r0];Enable SDRAM self-refreshmov r1,#16;wait until self-refresh is issued. may not be needed.0subs r1,r1,#1bne %B0ldr r0,=CLKCON;enter STOP mode.str r2,[r0]mov r1,#320subs r1,r1,#1;1) wait until the STOP mode is in effect.bne %B0;2) Or wait here until the CPU&Peripherals will be turned-off; Entering SLEEP mode, only the reset by wake-up is available.ldr r0,=REFRESH ;exit from SDRAM self refresh mode.str r3,[r0]MOV_PC_LRENTER_SLEEP;NOTE.;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.ldr r0,=REFRESHldr r1,[r0];r1=rREFRESHorr r1, r1, #BIT_SELFREFRESHstr r1, [r0];Enable SDRAM self-refreshmov r1,#16;Wait until self-refresh is issued,which may not be needed.0subs r1,r1,#1bne %B0ldrr1,=MISCCRldrr0,[r1]orrr0,r0,#(7<<17) ;Set SCLK0=0, SCLK1=0, SCKE=0.strr0,[r1]ldr r0,=CLKCON; Enter sleep modestr r2,[r0]b .;CPU will die here.WAKEUP_SLEEP;Release SCLKn after wake-up from the SLEEP mode.ldrr1,=MISCCRldrr0,[r1]bicr0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.strr0,[r1];Set memory control registers ldrr0,=SMRDATAldrr1,=BWSCON;BWSCON Addressaddr2, r0, #52;End address of SMRDATA0ldrr3, [r0], #4strr3, [r1], #4cmpr2, r0bne%B0mov r1,#2560subs r1,r1,#1;1) wait until the SelfRefresh is released.bne %B0ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-upldr r0,[r1]mov pc,r0LTORGHandlerFIQ HANDLER HandleFIQHandlerIRQ HANDLER HandleIRQHandlerUndef HANDLER HandleUndefHandlerSWI HANDLER HandleSWIHandlerDabort HANDLER HandleDabortHandlerPabort HANDLER HandlePabortIsrIRQsubsp,sp,#4 ;reserved for PCstmfdsp!,{r8-r9}ldrr9,=INTOFFSETldrr9,[r9]ldrr8,=HandleEINT0addr8,r8,r9,lsl #2ldrr8,[r8]strr8,[sp,#8]ldmfdsp!,{r8-r9,pc};=======; ENTRY;=======ResetHandlerldrr0,=WTCON ;watch dog disableldrr1,=0x0strr1,[r0]ldrr0,=INTMSKldrr1,=0xffffffff ;all interrupt disablestrr1,[r0]ldrr0,=INTSUBMSKldrr1,=0x7fff;all sub interrupt disablestrr1,[r0][ {FALSE}; GPBDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);; Led_Displayldrr0,=GPFCON ;JZ2440Ö¸ê¾μÆÎaGPF4/5/6ldrr1,=0x1500 ;GPF4/5/6 1ü½ÅéèÎaêä3östrr1,[r0]ldrr0,=GPFDAT;JZ2440Ö¸ê¾μÆÎaGPF4/5/6 éÏμçÖ¸ê¾μÆldrr1,=0x00 ;μãááGPF4/5/6strr1,[r0]];To reduce PLL lock time, adjust the LOCKTIME register.ldrr0,=LOCKTIMEldrr1,=0xffffffstrr1,[r0] [ PLL_ON_START; Added for confirm clock divide. for 2440.; Setting value Fclk:Hclk:Pclkldrr0,=CLKDIVNldrr1,=CLKDIV_VAL; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.strr1,[r0];[ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.;bl MMU_SetAsyncBusMode;|;bl MMU_SetFastBusMode; default value.;]; ==êÖ2áμú243ò3== ; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous ; bus mode using following instructions ;MMU_SetAsyncBusMode ;mrc p15,0,r0,c1,c0,0 ;orr r0,r0,#R1_nF:OR:R1_iA ;mcr p15,0,r0,c1,c0,0 [ CLKDIV_VAL>1 ; òa˼êÇ Fclk:Hclk 2»êÇ 1:1. mrc p15,0,r0,c1,c0,0 orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 | mrc p15,0,r0,c1,c0,0 bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF mcr p15,0,r0,c1,c0,0 ] ;Configure UPLLldrr0,=UPLLCONldrr1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) strr1,[r0]nop; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.nopnopnopnopnopnop;Configure MPLLldrr0,=MPLLCONldrr1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;Fin=16.9344MHzstrr1,[r0] ];Check if the boot is caused by the wake-up from SLEEP mode.ldrr1,=GSTATUS2ldrr0,[r1]tstr0,#0x2;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.bneWAKEUP_SLEEPEXPORT StartPointAfterSleepWakeUpStartPointAfterSleepWakeUp;Set memory control registers adrlr0,SMRDATAldrr1,=BWSCON;BWSCON Addressaddr2, r0, #52;End address of SMRDATA0ldrr3, [r0], #4strr3, [r1], #4cmpr2, r0bne%B0;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; When EINT0 is pressed, Clear SDRAM ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; check if EIN0 button is pressed ldrr0,=GPFCONldrr1,=0x0strr1,[r0]ldrr0,=GPFUPldrr1,=0xffstrr1,[r0]ldrr1,=GPFDATldrr0,[r1] bicr0,r0,#(0x1e<<1) ; bit cleartstr0,#0x1bne %F1; Clear SDRAM Start ldrr0,=GPFCONldrr1,=0x55aastrr1,[r0];ldrr0,=GPFUP;ldrr1,=0xff;strr1,[r0]ldrr0,=GPFDAT ;JZ2440Ö¸ê¾μÆÎaGPF4/5/6 ¼ì2aÖD¶Ïldrr1,=0x0strr1,[r0];LED=****mov r1,#0mov r2,#0mov r3,#0mov r4,#0mov r5,#0mov r6,#0mov r7,#0mov r8,#0ldrr9,=0x4000000 ;64MBldrr0,=0x300000000stmiar0!,{r1-r8}subsr9,r9,#32 bne%B0;Clear SDRAM End1 ;Initialize stack***lInitStacks;Check boot mode ldrr0, =BWSCONldrr0, [r0]andsr0, r0, #6;OM[1:0] != 0, NOR FLash bootbnecopy_proc_beg;do not read nand flash;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;¿éòÔÖ′DDldrr0,=GPFCON ;JZ2440Ö¸ê¾μÆÎaGPF4/5/6ldrr1,=0x1500 ;GPF4/5/6 1ü½ÅéèÎaêä3östrr1,[r0]ldrr0,=GPFDAT;JZ2440Ö¸ê¾μÆÎaGPF4/5 bootÆô¶ˉÑ¡Ôñldrr1,=0x60 ;μãááGPF4 0X60 GPF5 0x50 GPF6 0X30strr1,[r0]BL DELAYS adrr0, __ENTRY;OM[1:0] == 0, NAND FLash bootcmpr0, #0;if use Multi-ice, bnecopy_proc_beg;do not read nand flash for boot;nop;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Î′Ö′DD;===========================================================copy_myself;boot from nand flash[ {FALSE} ;2016.9.7 1:13bl CopyProgramFromNand|movr5, #NFCONFldrr0,=(1<<12)|(4<<8)|(1<<4)|(0<<0)strr0,[r5]ldrr0,=(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);strr0,[r5,#0x04]blReadNandIDmovr6, #0ldrr0, =0xec73cmpr5,r0beq%F1ldrr0, =0xec75cmpr5, r0beq%F1movr6, #11blReadNandStatusmovr8, #0ldrr9, =ResetEntry 2andsr0, r8, #0x1fbne%F3movr0, r8blCheckBadBlkcmpr0, #0addner8, r8, #32bne%F43movr0, r8movr1, r9blReadNandPageaddr9, r9, #512addr8, r8, #14cmpr8, #256 ;copy to sdram ;2016.9.7 1:13bcc%B2 ; now copy completed movr5, #NFCONF;DsNandFlashldrr0, [r5,#0x04]orrr0, r0, #0x01strr0, [r5,#0x04]ldrr0,=GPFCON ;JZ2440Ö¸ê¾μÆÎaGPF4/5/6ldrr1,=0x1500 ;GPF4/5/6 1ü½ÅéèÎaêä3östrr1,[r0]ldrr0,=GPFDAT;JZ2440Ö¸ê¾μÆÎaGPF4/5 nand to sdramldrr1,=0x50 ;μãááGPF4 0X60 GPF5 0x50 GPF6 0X30strr1,[r0]BL DELAYS ]ldrpc, =InitRam;ldrpc, =copy_proc_beg ;¸öèËèÏÎaInitRam ????????????????????????????? ;===========================================================copy_proc_beg ;adrr0, __ENTRYldrr2, BaseOfROMcmpr0, r2ldreqr0, TopOfROMbeqInitRamldr r3, TopOfROM0ldmiar0!, {r4-r7}stmiar2!, {r4-r7}cmpr2, r3bcc%B0subr2, r2, r3subr0, r0, r2InitRamldrr2, BaseOfBSSldrr3, BaseOfZero0cmpr2, r3ldrccr1, [r0], #4strccr1, [r2], #4bcc%B0movr0,#0ldrr3,EndOfBSS1cmpr2,r3strccr0, [r2], #4bcc%B1;ldrpc, =%F2;goto compiler address;=========================================================== ; Setup IRQ handler;ldrr0,=HandleIRQ ;This routine is needed;ldrr1,=IsrIRQ ;if there is not 'subs pc,lr,#4' at 0x18, 0x1c;strr1,[r0]; Setup IRQ handler;ldr r0,=HandleIRQ;This routine is needed;ldrr1,=IsrIRQ ;if there isn''t 'subs pc,lr,#4' at 0x18, 0x1c;ldr r1, =OS_CPU_IRQ_ISR ;modify by txf, for ucos ;str r1,[r0];/////////////////////////////////////////////////////////;×¢òa£¬òÔÏÂÕa¶Î¿éÄü2»Dèòa!!!!!!!!!!!!!!!!!!;//6.½«êy¾Y¶Î¿½±′μ½ramÖD ½«áã3õê¼»ˉêy¾Y¶ÎÇåáã ìøèëCóïÑÔμÄmainoˉêyÖ′DDμ½Õa2½½áêøbootloader3õ2½òyμ¼½áêø;If main() is used, the variable initialization will be done in __main().;[ {FALSE};by tinko -- ???????tinko??,????????? ; [ :LNOT:USE_MAIN ;initialized {FALSE} ;;Copy and paste RW data/zero initialized data;ldrr0, =|Image$$RO$$Limit| ; Get pointer to ROM data;ldrr1, =|Image$$RW$$Base| ; and RAM copy;ldrr3, =|Image$$ZI$$Base|;;;Zero init base => top of initialised data;cmpr0, r1 ; Check that they are different;beq%F2;1;cmpr1, r3 ; Copy init data;ldrccr2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4;strccr2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4;bcc%B1;2;ldrr1, =|Image$$ZI$$Limit| ; Top of zero init segment;movr2, #0;3;cmpr3, r1 ; Zero init;strccr2, [r3], #4;bcc%B3;];];=============================================================;bl main;;============================================================= [ :LNOT:THUMBCODE ;;if thumbcode={false} bl main L logic?? ldrr0,=GPFCON ;JZ2440Ö¸ê¾μÆÎaGPF4/5/6ldrr1,=0x1500 ;GPF4/5/6 1ü½ÅéèÎaêä3östrr1,[r0]ldrr0,=GPFDAT;JZ2440Ö¸ê¾μÆÎaGPF6 bl MAINÇ°ldrr1,=0x30 ;μãááGPF4 0X60 GPF5 0x50 GPF6 0X30strr1,[r0]BL DELAYS IMPORT Main ; The main entry of mon programLDR PC,=Main ;blMain;Don''t use main() because ...... ½øèëmainoˉêy b. ] [ THUMBCODE ;for start-up code for Thumb mode orrlr,pc,#1 bxlr CODE16 LDR PC,=Main;blMain;Don''t use main() because ...... b.CODE32 ]DELAYS MOV R7,#0x00002000 ;????DELAYS_L1SUBS R7,R7,#1 ;R7 = R7-1 BNE DELAYS_L1 ;?R7-1?????0,???0??? MOV PC,LR ;?? ;function initializing stacksInitStacks;Don''t use DRAM,such as stmfd,ldmfd......;SVCstack is initialized before;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'mrsr0,cpsrbicr0,r0,#MODEMASKorrr1,r0,#UNDEFMODE|NOINTmsrcpsr_cxsf,r1;UndefModeldrsp,=UndefStack; UndefStack=0x33FF_5C00orrr1,r0,#ABORTMODE|NOINTmsrcpsr_cxsf,r1;AbortModeldrsp,=AbortStack; AbortStack=0x33FF_6000orrr1,r0,#IRQMODE|NOINTmsrcpsr_cxsf,r1;IRQModeldrsp,=IRQStack; IRQStack=0x33FF_7000orrr1,r0,#FIQMODE|NOINTmsrcpsr_cxsf,r1;FIQModeldrsp,=FIQStack; FIQStack=0x33FF_8000bicr0,r0,#MODEMASK|NOINTorrr1,r0,#SVCMODEmsrcpsr_cxsf,r1;SVCModeldrsp,=SVCStack; SVCStack=0x33FF_5800;USER mode has not be initialized.movpc,lr;The LR register won''t be valid if the current mode is not SVC mode.;=============================================================;Nand Flash;;=============================================================;[ {TRUE};|ReadNandIDmov r7,#NFCONFldr r0,[r7,#4];NFChipEn();bic r0,r0,#0x02str r0,[r7,#4]mov r0,#0x90;WrNFCmd(RdIDCMD);strb r0,[r7,#8] ;NFCMDmov r4,#0;WrNFAddr(0);strb r4,[r7,#0x0c];NFADDR1;while(NFIsBusy());ldr r0,[r7,#0x20];NFSTATtst r0,#1beq %B1ldrb r0,[r7,#0x10];NFDATA id = RdNFDat()<<8;mov r0,r0,lsl #8ldrb r1,[r7,#0x10];id |= RdNFDat();orr r5,r1,r0ldr r0,[r7,#4];NFChipDs();orr r0,r0,#0x02str r0,[r7,#4]mov pc,lrReadNandStatusmov r7,#NFCONFldr r0,[r7,#4];NFChipEn();bic r0,r0,#0x02str r0,[r7,#4]mov r0,#0x70;WrNFCmd(QUERYCMD);strb r0,[r7,#8] ;NFCMDldrb r1,[r7,#0x10];r1 = RdNFDat();ldr r0,[r7,#4];NFChipDs();orr r0,r0,#0x02str r0,[r7,#4]mov pc,lrWaitNandBusymov r0,#0x70;WrNFCmd(QUERYCMD);mov r1,#NFCONFstrb r0,[r1,#8] ;NFCMD1;while(!(RdNFDat()&0x40));ldrb r0,[r1,#0x10] ;NFDATAtst r0,#0x40beq %B1mov r0,#0;WrNFCmd(READCMD0);strb r0,[r1,#8]mov pc,lrCheckBadBlkmovr7, lrmovr5, #NFCONFbicr0, r0, #0x1f;addr &= ~0x1f;ldr r1,[r5,#4];NFChipEn()bic r1,r1,#0x02str r1,[r5,#4]mov r1,#0x50;WrNFCmd(READCMD2)strb r1,[r5,#8] ;NFCMDmov r1, #6strb r1,[r5,#0x0c];WrNFAddr(6)strb r0,[r5,#0x0c];WrNFAddr(addr)mov r1,r0,lsr #8;WrNFAddr(addr>>8)strb r1,[r5,#0x0c]cmp r6,#0;if(NandAddr)movne r0,r0,lsr #16;WrNFAddr(addr>>16)strneb r0,[r5,#0x0c]blWaitNandBusy;WaitNFBusy()ldrbr0, [r5,#0x10];RdNFDat()subr0, r0, #0xffmov r1,#0;WrNFCmd(READCMD0)strb r1,[r5,#8]ldr r1,[r5,#4];NFChipDs()orr r1,r1,#0x02str r1,[r5,#4]movpc, r7ReadNandPagemov r7,lrmov r4,r1mov r5,#NFCONFldr r1,[r5,#4];NFChipEn()bic r1,r1,#0x02 str r1,[r5,#4]mov r1,#0;WrNFCmd(READCMD0)strb r1,[r5,#8]strb r1,[r5,#0x0c];WrNFAddr(0)strb r0,[r5,#0x0c];WrNFAddr(addr)mov r1,r0,lsr #8;WrNFAddr(addr>>8)strb r1,[r5,#0x0c]cmp r6,#0;if(NandAddr)movne r0,r0,lsr #16;WrNFAddr(addr>>16)strneb r0,[r5,#0x0c]ldr r0,[r5,#0];InitEcc()orr r0,r0,#0x0010str r0,[r5,#0]bl WaitNandBusy;WaitNFBusy()mov r0,#0;for(i=0; i<512; i++)1ldrb r1,[r5,#0x10];buf = RdNFDat()strb r1,[r4,r0]add r0,r0,#1bic r0,r0,#0x10000cmp r0,#0x200bcc %B1ldr r0,[r5,#4];NFChipDs()orr r0,r0,#0x02str r0,[r5,#4]mov pc,r7;];=====================================================================; Clock division test; Assemble code, because VSYNC time is very short;=====================================================================EXPORT CLKDIV124EXPORT CLKDIV144CLKDIV124ldr r0, = CLKDIVNldr r1, = 0x3; 0x3 = 1:2:4str r1, [r0];wait until clock is stablenopnopnopnopnopldr r0, = REFRESHldr r1, [r0]bicr1, r1, #0xffbicr1, r1, #(0x7<<8)orrr1, r1, #0x470; REFCNT135str r1, [r0]nopnopnopnopnopmov pc, lrCLKDIV144ldr r0, = CLKDIVNldr r1, = 0x4; 0x4 = 1:4:4str r1, [r0];wait until clock is stablenopnopnopnopnopldr r0, = REFRESHldr r1, [r0]bicr1, r1, #0xffbicr1, r1, #(0x7<<8)orrr1, r1, #0x630; REFCNT675 - 1520str r1, [r0]nopnopnopnopnopmov pc, lr LTORGSMRDATA DATA; Memory configuration should be optimized for best performance; The following parameter is not optimized.; Memory access cycle parameter strategy; 1) The memory settings is safe parameters even at HCLK=75Mhz.; 2) SDRAM refresh period is for HCLK<=75Mhz.DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC));GCS0DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC));GCS1DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));GCS2DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC));GCS3DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC));GCS4DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC));GCS5DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN));GCS6DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN));GCS7DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)DCD 0x32;SCLK power saving mode, BANKSIZE 128M/128MDCD 0x30;MRSR6 CL=3clkDCD 0x30;MRSR7 CL=3clkBaseOfROMDCD |Image$$ER_ROM1$$Base|TopOfROMDCD |Image$$ER_ROM1$$Limit|BaseOfBSSDCD |Image$$RW_RAM1$$Base|BaseOfZeroDCD |Image$$RW_RAM1$$Base|EndOfBSSDCD |Image$$RW_RAM1$$Limit|ALIGNAREA RamData, DATA, READWRITE^ _ISR_STARTADDRESS; _ISR_STARTADDRESS=0x33FF_FF00HandleReset # 4HandleUndef # 4HandleSWI# 4HandlePabort # 4HandleDabort # 4HandleReserved # 4HandleIRQ# 4HandleFIQ# 4;Don''t use the label 'IntVectorTable',;The value of IntVectorTable is different with the address you think it may be.;IntVectorTable;@0x33FF_FF20HandleEINT0# 4HandleEINT1# 4HandleEINT2# 4HandleEINT3# 4HandleEINT4_7# 4HandleEINT8_23# 4HandleCAM# 4; Added for 2440.HandleBATFLT# 4HandleTICK# 4HandleWDT# 4HandleTIMER0 # 4HandleTIMER1 # 4HandleTIMER2 # 4HandleTIMER3 # 4HandleTIMER4 # 4HandleUART2 # 4;@0x33FF_FF60HandleLCD # 4HandleDMA0# 4HandleDMA1# 4HandleDMA2# 4HandleDMA3# 4HandleMMC# 4HandleSPI0# 4HandleUART1# 4HandleNFCON# 4; Added for 2440.HandleUSBD# 4HandleUSBH# 4HandleIIC# 4HandleUART0 # 4HandleSPI1 # 4HandleRTC # 4HandleADC # 4;@0x33FF_FFA0END |
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2个回答
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keil 的一些设置,不知是否有错,不过编译时可以通过的。
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只有小组成员才能发言,加入小组>>
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移植了freeRTOS到STMf103之后显示没有定义的原因?
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使用eim外接fpga可是端口一点反应都没有有没有大哥指点一下啊
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请教大神怎样去解决iMX6Q在linux3.0.35内核上做AP失败的问题呢
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