This document provides the information needed by platform and system design teams to integration of Logic Analyzer Probing for PCI Express into their designs.
两位无符号二进制数比较器
module Verilog(Y,A,B);
input [1:0] A ;
wire [1:0] A ;
input [1:0] B ;
wire [1:0] B ;
output [2:0] Y ;
reg [2:0] Y ;
always @ (A or B)
begin ...