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Avrumw,
1) I cannot determine why the source clock starts at a BUFG other than I have hand instantiated a BUFG from this clock pin in order to split it at the c ...
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Avrumw,
Thanks for the feedback. Going back to the picture above, I need a -source to ensure that we are picking up the correct input as I have a set_case_ana ...
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More info, hope it isn't overwhelming.
If I define the p1750_hclk as:
create_generated_clock -name p1750_hclk \
-master_clock [get_clocks ClockReset_inst/cl ...
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Avrumw,
Well after ripping out my clocking network and starting over I finally have the design P&R again. I still have a problem that I cannot seem to get the ...