aic3204做从设备，制后没有声音出来是哪里的问题？

TLV320AIC3204 codec，请帮忙提供一份在调试板上声音正常的寄存器配置，
当前环境：aic3204做从设备，mclk=12.288M, 采样48K, 接的是In3R/In3L，录制后没有声音出来。
/* Configure AIC3204 */
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
aic3204_write(IIC_device_addr[num], 1, 0x1); // Reset Codec
mdelay(20);
aic3204_write(IIC_device_addr[num], 0, 0x1); // Select to page 1
aic3204_write(IIC_device_addr[num], 1, 0x8); // DisabLED weak connection of AVDD with DVDD
aic3204_write(IIC_device_addr[num], 2, 0x1); // Enable analog Blocks, use LDO power (is LDO power being used? If it is, then this register needs to be set correclty to use LDO).
/* PLL and clocks config and Power Up */
// mclk=12.288m, fs=48K, config: p=R=1, j=7, D=0, madc=2, nadc=7, aosr=128
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
///aic3204_write(IIC_device_addr[num], 27, 0x4d); // BCLK and WCLK is set as output from AIC3204(Master) 00: audio InteRFace = dsp
aic3204_write(IIC_device_addr[num], 27, 0x1); // BCLK and WCLK is set as input AIC3204(slave) 00: audio InteRFace = i2s
aic3204_write(IIC_device_addr[num], 28, 0x0); // Data ofset = 0
aic3204_write(IIC_device_addr[num], 4, 0x3); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
aic3204_write(IIC_device_addr[num], 6, 0x7); // **PLL setting: J=7
aic3204_write(IIC_device_addr[num], 7, 0x0); // PLL setting: HI_BYTE(D)
aic3204_write(IIC_device_addr[num], 8, 0x0); // PLL setting: LO_BYTE(D)
aic3204_write(IIC_device_addr[num], 30, 0x80); // For 32 bit clocks per frame in Master mode ONLY (make sure that BCLK >= [ (# bits per channel) * 2 ]
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
// For 48 KHz sampling
aic3204_write(IIC_device_addr[num], 5, 0x91); // PLL setting: Power up PLL, P=1 and R=1
aic3204_write(IIC_device_addr[num], 13, 0x01); // Hi_Byte(DOSR) for DOSR = 256 decimal or 0x01080 DAC oversamppling
aic3204_write(IIC_device_addr[num], 14, 0x00); // Lo_Byte(DOSR) for DOSR = 256 decimal or 0x0100
aic3204_write(IIC_device_addr[num], 20, 0x00); // AOSR for AOSR = 256 decimal or 0x0000 for decimation filters 1 to 6
aic3204_write(IIC_device_addr[num], 11, 0x87); // Power up NDAC and set NDAC value to 3 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 12, 0x82); // Power up MDAC and set MDAC value to 8 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 18, 0x82); // Power up NADC and set NADC value to 8 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 19, 0x87); // Power up MADC and set MADC value to 6 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 20, 0x80); // AOSR = 128 (default).
aic3204_write(IIC_device_addr[num], 60, 0x19); // Power up PRB_P25 for beep generator Selects the ADC (recording) signal processing block
aic3204_write(IIC_device_addr[num], 61, 0x01); // ADC Singal Processing Block PRB_R1 ADC Signal Processing Block Control Register
aic3204_write(IIC_device_addr[num], 48, 0xff); // Power up MADC and set MADC value to 6 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 49, 0xff); // Power up PRB_P25 for beep generator
/* DAC ROUTING and Power Up */
aic3204_write(IIC_device_addr[num], 0, 0x01); // Select page 1
aic3204_write(IIC_device_addr[num], 12, 0x08); // LDAC AFIR routed to HPL
aic3204_write(IIC_device_addr[num], 13, 0x08); // RDAC AFIR routed to HPR &&&&&&&
aic3204_write(IIC_device_addr[num], 14, 0x00); // Right Channel DAC reconstruction filter's negative terminal is not routed to LOL
aic3204_write(IIC_device_addr[num], 15, 0x00); // Right Channel DAC reconstruction filter output is not routed to LOR
aic3204_write(IIC_device_addr[num], 0, 0x00); // Select page 0
aic3204_write(IIC_device_addr[num], 64, 0x02); // Left vol=right vol
aic3204_write(IIC_device_addr[num], 65, 0x00); // Left DAC gain to 0dB VOL; Right tracks Left
aic3204_write(IIC_device_addr[num], 66, 0x81); // right mute
aic3204_write(IIC_device_addr[num], 63, 0xd4); // Power up left,right data paths and set channel
aic3204_write(IIC_device_addr[num], 0, 0x01); // Select page 1
aic3204_write(IIC_device_addr[num], 20, 0x69); // Soft Step, De-pop, 6 time constants, 6k ohm.
aic3204_write(IIC_device_addr[num], 16, 0x1d); // Unmute HPL , 29dB gain
aic3204_write(IIC_device_addr[num], 17, 0x3a); // Unmute HPR , -6dB gain
aic3204_write(IIC_device_addr[num], 9, 0x30); // Power up HPL,HPR
aic3204_write(IIC_device_addr[num], 10, 0x33); // HP powered from LDOIN, CM voltage = 1.65V
aic3204_write(IIC_device_addr[num], 0, 0x00); // Select page 0
mdelay(20); // Wait
aic3204_write(IIC_device_addr[num], 16, 15); // Unmute HPL set gain
aic3204_write(IIC_device_addr[num], 17, 00); // Unmute HPR set gain
/* ADC ROUTING and Power Up */
aic3204_write(IIC_device_addr[num], 0, 1 ); // Select page 1
///aic3204_write(IIC_device_addr[num], 52, 0x10 ); //IN2L is routed to Left MICPGA with 40K resistance
///aic3204_write(IIC_device_addr[num], 55, 0x00 ); //IN2R is not routed to Right MICPGA
aic3204_write(IIC_device_addr[num], 52, 0x04); //IN3L is routed to Left MICPGA with 10K resistance
aic3204_write(IIC_device_addr[num], 55, 0x04); //IN3R is not routed to Right MICPGA
aic3204_write(IIC_device_addr[num], 54, 0x03); // CM is routed to Left MICPGA via CM2L with 40K resistance
aic3204_write(IIC_device_addr[num], 57, 0xC0); // CM is routed to right MICPGA via CM2L with 40K resistance
///aic3204_write(IIC_device_addr[num], 59, 0x80); // MIC_PGA_L unmute
///aic3204_write(IIC_device_addr[num], 60, 0x80); // MIC_PGA_R unmute
aic3204_write(IIC_device_addr[num], 59, 0x0C); // MIC_PGA_L unmute
aic3204_write(IIC_device_addr[num], 60, 0x0C); // MIC_PGA_R unmute
aic3204_write(IIC_device_addr[num], 0, 0); // Select page 0
///aic3204_write(IIC_device_addr[num], 81, 0xa0); // Powerup Left and Right ADC
///aic3204_write(IIC_device_addr[num], 82, 0x4); // Unmute Left and Right ADC
aic3204_write(IIC_device_addr[num], 81, 0xC0); // Powerup Left and Right ADC
aic3204_write(IIC_device_addr[num], 82, 0x00); // Unmute Left and Right ADC

陈军

2024-10-11 11:32:17

DOSR=128，R_13应为0x00，R_14应为0x80，
关于处理块的选择，播放的话选择PRB_P1到PRB_P25，录音的话选择PRB_R1到PRB_R18
您是要录音后，再播放出来吗，那么您还需要配置DAC to HPL的相关寄存器

根据您的描述，您正在使用TLV320AIC3204作为从设备，并且您已经提供了一些寄存器配置。在这种情况下，录制后没有声音出来可能是由于以下原因：

1. 配置错误：请确保您已经正确配置了AIC3204的寄存器。以下是一份在调试板上声音正常的寄存器配置示例：

```c
/* Configure AIC3204 */
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
aic3204_write(IIC_device_addr[num], 1, 0x1); // Reset Codec
mdelay(20);
aic3204_write(IIC_device_addr[num], 0, 0x1); // Select page 1
aic3204_write(IIC_device_addr[num], 1, 0x8); // DisabLED weak connection of AVDD with DVDD
aic3204_write(IIC_device_addr[num], 0, 0x2); // Select page 2
aic3204_write(IIC_device_addr[num], 2, 0x0); // Set sample rate to 48kHz
aic3204_write(IIC_device_addr[num], 3, 0x0); // Set format to I2S
aic3204_write(IIC_device_addr[num], 4, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 5, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 6, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 7, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 8, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 9, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 10, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 11, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 12, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 13, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 14, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 15, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 16, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 17, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 18, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 19, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 20, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 21, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 22, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 23, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 24, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 25, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 26, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 27, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 28, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 29, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 30, 0x0); // Set clock divider
aic3204_write(IIC_device_addr[num], 31, 0x0); // Set clock divider

颜立歆

回帖（2）

陈军

王彬

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