uart2axi_master_intf程序源码：
/***************************************************
* Module Name : uart2axi_master_intf
* Engineer : Huangruigui
* Target Device :
* Tool versions :
* Create Date :
* Revision : v1.0
* Description :
**************************************************/
module uart2axi_master_intf #(
parameter M_AXI_ADDR_WIDTH = 8'd32,
parameter M_AXI_DATA_WIDTH = 8'd32,
parameter RX_TOTAL_BYTE = 8'd9, // 串口接收到9byte数据开始工作
parameter TX_TOTAL_BYTE = 8'd4 // 串口发送4byte数据给上位机
)(
// Global Clock Signal
input wire m_axi_aclk, // 模块基准时钟，100MHz
input wire m_axi_aresetn, // 模块复位信号，低电平有效
// Master Write Addr Interface
output reg m_axi_awvalid,
input wire m_axi_awready,
output wire [M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
// Master Write Date Interface
output reg m_axi_wvalid,
input wire m_axi_wready,
output wire [M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
// Master Read Addr Interface
output reg m_axi_arvalid,
input wire m_axi_arready,
output wire [M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
// Master Read Date Interface
output wire m_axi_rready,
input wire m_axi_rvalid,
input wire [M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
// Master Response Interface
output reg m_axi_bready,
input wire m_axi_bvalid,
input wire [1:0] m_axi_bresp,
input wire uart_write,
input wire [M_AXI_ADDR_WIDTH-1:0] uart_write_addr,
input wire [M_AXI_DATA_WIDTH-1:0] uart_write_data,
input wire uart_read,
input wire [M_AXI_ADDR_WIDTH-1:0] uart_read_addr,
output reg uart_tx_en,
output reg [M_AXI_DATA_WIDTH-1:0] uart_tx_data
);
//parameter define
localparam OKAY = 2'b00,
EXOKAY = 2'b01,
SLVERR = 2'b10,
DECERR = 2'b11;
assign m_axi_wstrb = {(M_AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wdata = uart_write_data;
assign m_axi_awaddr = uart_write_addr;
assign m_axi_araddr = uart_read_addr;
assign m_axi_rready = 1;
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_bready <= 0;
else if(m_axi_wvalid & m_axi_wready)
m_axi_bready <= 1;
else if(m_axi_bvalid & (m_axi_bresp == OKAY))
m_axi_bready <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_awvalid <= 0;
else if(uart_write)
m_axi_awvalid <= 1;
else if(m_axi_awready)
m_axi_awvalid <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_wvalid <= 0;
else if(m_axi_awvalid & m_axi_awready)
m_axi_wvalid <= 1;
else if(m_axi_wready)
m_axi_wvalid <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_arvalid <= 0;
else if(uart_read)
m_axi_arvalid <= 1;
else if(m_axi_arready)
m_axi_arvalid <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
begin
uart_tx_en <= 0;
uart_tx_data <= 0;
end
else if(m_axi_rvalid & m_axi_rready)
begin
uart_tx_en <= 1;
uart_tx_data <= m_axi_rdata;
end
else if(uart_write)
begin
uart_tx_en <= 1;
uart_tx_data <= uart_write_data; // 将写数据发送回上位机作为响应
end
else
uart_tx_en <= 0;
end
endmodule
//*****************文件结束**************************
整个模块测试文件
/***************************************************
* Module Name : uart2axi_master_tb
* Engineer : Huangruigui
* Target Device :
* Tool versions :
* Create Date :
* Revision : v1.0
* Description :
**************************************************/
`timescale 1ns/1ns
module uart2axi_master_tb;
// parameter define
parameter M_AXI_ADDR_WIDTH = 8'd32;
parameter M_AXI_DATA_WIDTH = 8'd32;
parameter BAUD_SET = 16'd10416; // 波特率设置，默认9600
parameter RX_TOTAL_BYTE = 8'd9; // 串口接收到9byte数据开始工作
parameter TX_TOTAL_BYTE = 8'd4; // 串口发送4byte数据给上位机
parameter WRITE_BIT = 5'd1; // 设置最高位1为写操作
parameter READ_BIT = 5'd2;
reg sys_clk;
reg sys_rst_n;
reg tx_en;
reg [7:0] tx_data;
wire tx_done ;
wire uart_tx ;
wire m_axi_awvalid;
reg m_axi_awready;
wire [M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
wire m_axi_wvalid;
reg m_axi_wready;
wire [M_AXI_DATA_WIDTH-1:0] m_axi_wdata;
wire [M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb;
wire m_axi_arvalid;
reg m_axi_arready;
wire [M_AXI_ADDR_WIDTH-1:0] m_axi_araddr;
wire m_axi_rready;
reg m_axi_rvalid;
reg [M_AXI_DATA_WIDTH-1:0] m_axi_rdata;
reg [1:0] m_axi_rresp;
wire m_axi_bready;
reg m_axi_bvalid;
reg [1:0] m_axi_bresp;
initial sys_clk = 1;
always #5 sys_clk = ~sys_clk;
initial begin
sys_rst_n = 0;
tx_en = 0;
tx_data = 0;
m_axi_awready = 1;
m_axi_wready = 1;
m_axi_arready = 1;
m_axi_rresp = 2'b00;
m_axi_rvalid = 0;
m_axi_rdata = 0;
m_axi_bvalid = 1;
m_axi_bresp = 2'b00;
#201;
sys_rst_n = 1;
#20;
@(posedge sys_clk)
#100;
tx_data = 0; // 测试写操作
repeat(9)
begin
tx_en = 1;
tx_data = tx_data + 1;
#10;
tx_en = 0;
wait(tx_done);
#100;
end
#100;
if((m_axi_awaddr == 32'h02030405) & (m_axi_wdata == 32'h06070809))
$display("test success");
else
$display("test fail");
#1000;
tx_data = 1; // 测试读操作
repeat(9)
begin
tx_en = 1;
tx_data = tx_data + 1;
#10;
tx_en = 0;
wait(tx_done);
#100;
end
if(m_axi_araddr == 32'h03040506)
$display("test success");
else
$display("test fail");
#100;
m_axi_rvalid = 1; // 测试串口发送
m_axi_rdata = 32'h12345678;
#10;
m_axi_rvalid = 0;
wait(uart2axi_master.uart2axi_master_logic.byte_matching.tx_conduct.uart_tx_done);
#1000;
$stop;
end
uart_tx_logic #(
.BAUD_SET ( BAUD_SET )
)uart_tx_logic(
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.tx_en ( tx_en ),
.tx_data ( tx_data ),
.tx_done ( tx_done ),
.uart_tx ( uart_tx )
);
uart2axi_master #(
.M_AXI_ADDR_WIDTH ( M_AXI_ADDR_WIDTH),
.M_AXI_DATA_WIDTH ( M_AXI_DATA_WIDTH),
.RX_TOTAL_BYTE ( RX_TOTAL_BYTE ),
.TX_TOTAL_BYTE ( TX_TOTAL_BYTE )
)uart2axi_master(
.m_axi_aclk ( sys_clk ),
.m_axi_aresetn ( sys_rst_n ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awready ( m_axi_awready ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wready ( m_axi_wready ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_arready ( m_axi_arready ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_rready ( m_axi_rready ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rdata ( m_axi_rdata ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_bready ( m_axi_bready ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_bresp ( m_axi_bresp ),
.UART_RX ( uart_tx ),
.UART_TX ( )
);
endmodule
//*****************文件结束*************************
uart2axi_master_intf程序源码：
/***************************************************
* Module Name : uart2axi_master_intf
* Engineer : Huangruigui
* Target Device :
* Tool versions :
* Create Date :
* Revision : v1.0
* Description :
**************************************************/
module uart2axi_master_intf #(
parameter M_AXI_ADDR_WIDTH = 8'd32,
parameter M_AXI_DATA_WIDTH = 8'd32,
parameter RX_TOTAL_BYTE = 8'd9, // 串口接收到9byte数据开始工作
parameter TX_TOTAL_BYTE = 8'd4 // 串口发送4byte数据给上位机
)(
// Global Clock Signal
input wire m_axi_aclk, // 模块基准时钟，100MHz
input wire m_axi_aresetn, // 模块复位信号，低电平有效
// Master Write Addr Interface
output reg m_axi_awvalid,
input wire m_axi_awready,
output wire [M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
// Master Write Date Interface
output reg m_axi_wvalid,
input wire m_axi_wready,
output wire [M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
// Master Read Addr Interface
output reg m_axi_arvalid,
input wire m_axi_arready,
output wire [M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
// Master Read Date Interface
output wire m_axi_rready,
input wire m_axi_rvalid,
input wire [M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
// Master Response Interface
output reg m_axi_bready,
input wire m_axi_bvalid,
input wire [1:0] m_axi_bresp,
input wire uart_write,
input wire [M_AXI_ADDR_WIDTH-1:0] uart_write_addr,
input wire [M_AXI_DATA_WIDTH-1:0] uart_write_data,
input wire uart_read,
input wire [M_AXI_ADDR_WIDTH-1:0] uart_read_addr,
output reg uart_tx_en,
output reg [M_AXI_DATA_WIDTH-1:0] uart_tx_data
);
//parameter define
localparam OKAY = 2'b00,
EXOKAY = 2'b01,
SLVERR = 2'b10,
DECERR = 2'b11;
assign m_axi_wstrb = {(M_AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wdata = uart_write_data;
assign m_axi_awaddr = uart_write_addr;
assign m_axi_araddr = uart_read_addr;
assign m_axi_rready = 1;
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_bready <= 0;
else if(m_axi_wvalid & m_axi_wready)
m_axi_bready <= 1;
else if(m_axi_bvalid & (m_axi_bresp == OKAY))
m_axi_bready <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_awvalid <= 0;
else if(uart_write)
m_axi_awvalid <= 1;
else if(m_axi_awready)
m_axi_awvalid <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_wvalid <= 0;
else if(m_axi_awvalid & m_axi_awready)
m_axi_wvalid <= 1;
else if(m_axi_wready)
m_axi_wvalid <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
m_axi_arvalid <= 0;
else if(uart_read)
m_axi_arvalid <= 1;
else if(m_axi_arready)
m_axi_arvalid <= 0;
end
always@(posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(!m_axi_aresetn)
begin
uart_tx_en <= 0;
uart_tx_data <= 0;
end
else if(m_axi_rvalid & m_axi_rready)
begin
uart_tx_en <= 1;
uart_tx_data <= m_axi_rdata;
end
else if(uart_write)
begin
uart_tx_en <= 1;
uart_tx_data <= uart_write_data; // 将写数据发送回上位机作为响应
end
else
uart_tx_en <= 0;
end
endmodule
//*****************文件结束**************************
整个模块测试文件
/***************************************************
* Module Name : uart2axi_master_tb
* Engineer : Huangruigui
* Target Device :
* Tool versions :
* Create Date :
* Revision : v1.0
* Description :
**************************************************/
`timescale 1ns/1ns
module uart2axi_master_tb;
// parameter define
parameter M_AXI_ADDR_WIDTH = 8'd32;
parameter M_AXI_DATA_WIDTH = 8'd32;
parameter BAUD_SET = 16'd10416; // 波特率设置，默认9600
parameter RX_TOTAL_BYTE = 8'd9; // 串口接收到9byte数据开始工作
parameter TX_TOTAL_BYTE = 8'd4; // 串口发送4byte数据给上位机
parameter WRITE_BIT = 5'd1; // 设置最高位1为写操作
parameter READ_BIT = 5'd2;
reg sys_clk;
reg sys_rst_n;
reg tx_en;
reg [7:0] tx_data;
wire tx_done ;
wire uart_tx ;
wire m_axi_awvalid;
reg m_axi_awready;
wire [M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
wire m_axi_wvalid;
reg m_axi_wready;
wire [M_AXI_DATA_WIDTH-1:0] m_axi_wdata;
wire [M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb;
wire m_axi_arvalid;
reg m_axi_arready;
wire [M_AXI_ADDR_WIDTH-1:0] m_axi_araddr;
wire m_axi_rready;
reg m_axi_rvalid;
reg [M_AXI_DATA_WIDTH-1:0] m_axi_rdata;
reg [1:0] m_axi_rresp;
wire m_axi_bready;
reg m_axi_bvalid;
reg [1:0] m_axi_bresp;
initial sys_clk = 1;
always #5 sys_clk = ~sys_clk;
initial begin
sys_rst_n = 0;
tx_en = 0;
tx_data = 0;
m_axi_awready = 1;
m_axi_wready = 1;
m_axi_arready = 1;
m_axi_rresp = 2'b00;
m_axi_rvalid = 0;
m_axi_rdata = 0;
m_axi_bvalid = 1;
m_axi_bresp = 2'b00;
#201;
sys_rst_n = 1;
#20;
@(posedge sys_clk)
#100;
tx_data = 0; // 测试写操作
repeat(9)
begin
tx_en = 1;
tx_data = tx_data + 1;
#10;
tx_en = 0;
wait(tx_done);
#100;
end
#100;
if((m_axi_awaddr == 32'h02030405) & (m_axi_wdata == 32'h06070809))
$display("test success");
else
$display("test fail");
#1000;
tx_data = 1; // 测试读操作
repeat(9)
begin
tx_en = 1;
tx_data = tx_data + 1;
#10;
tx_en = 0;
wait(tx_done);
#100;
end
if(m_axi_araddr == 32'h03040506)
$display("test success");
else
$display("test fail");
#100;
m_axi_rvalid = 1; // 测试串口发送
m_axi_rdata = 32'h12345678;
#10;
m_axi_rvalid = 0;
wait(uart2axi_master.uart2axi_master_logic.byte_matching.tx_conduct.uart_tx_done);
#1000;
$stop;
end
uart_tx_logic #(
.BAUD_SET ( BAUD_SET )
)uart_tx_logic(
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.tx_en ( tx_en ),
.tx_data ( tx_data ),
.tx_done ( tx_done ),
.uart_tx ( uart_tx )
);
uart2axi_master #(
.M_AXI_ADDR_WIDTH ( M_AXI_ADDR_WIDTH),
.M_AXI_DATA_WIDTH ( M_AXI_DATA_WIDTH),
.RX_TOTAL_BYTE ( RX_TOTAL_BYTE ),
.TX_TOTAL_BYTE ( TX_TOTAL_BYTE )
)uart2axi_master(
.m_axi_aclk ( sys_clk ),
.m_axi_aresetn ( sys_rst_n ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awready ( m_axi_awready ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wready ( m_axi_wready ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_arready ( m_axi_arready ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_rready ( m_axi_rready ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rdata ( m_axi_rdata ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_bready ( m_axi_bready ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_bresp ( m_axi_bresp ),
.UART_RX ( uart_tx ),
.UART_TX ( )
);
endmodule
//*****************文件结束*************************
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