我有一个针对spartan-6（LX45）的项目，该项目在ISE 12.2中没有出现任何问题。
最近升级到ISE 14.7项目不再正确构建。
问题是BRAM没有正确初始化。
此项目中BRAM使用的方法是通过参数化宽度并使用.mif文件作为初始值来推断它。
随附的是重现问题的项目。
此zip文件必须解压缩到C：
FPGA_Design，或者您可以手动重建和重新引用这些文件。一个项目用于ISE 12.2，另一个用于ISE 14.7，完全相同的代码，但每个项目应该从其各自的ISE运行
版。
使用两个版本的行为模拟正确匹配。
事情出错的第一个迹象是翻译后模拟。
12.2版本有效，而14.7没有。
它从那里螺旋下来。
我试图通过
仿真使这个可以重现，但是对于模拟设置没有任何顾虑，它在构建在tartet上时显示相同的东西。
有趣的是，BROM（只读BRAM）似乎很好。
它只是BRAM（读/写）没有。
任何帮助或类似问题表示赞赏。
我不认为这与众所周知的9K Block RAM Ini
tialization问题有关。
FPGA_Design.zip 239 KB
以上来自于谷歌翻译
以下为原文
I have a project targeting the spartan-6 (LX45) that has been working with no problems being built in ISE 12.2. Recently upgrading to ISE 14.7 the project no longer builds correctly. The issue is that the BRAM is not initialized correctly. The method for BRAM usage in this project is to infer it by parameterizing the widths and using a .mif file for initial values.
Attached are projects that reproduce the problem. This zip file must be unzipped to C:FPGA_Design, or you can manually rebuild and re-referrence the files.
One project is for ISE 12.2 and the other for ISE 14.7, exact same code but each project should be run from its respective ISE version. The behavioral simulation using both versions matches correctly. The first sign of things going wrong is in the post-translate simulation. The 12.2 version works while the 14.7 does not. It spirals down from there. I tried to make this reproduceable from simulation, but just so there are no concerns about simulation setup it shows the same things when built on a tartet.
Interestingly enough BROM (Read only BRAM) seems to initalize fine. Its just the BRAM (read/write) that does not.
Any help or similar issues is appreciated. I don't think this is related to the well known 9K Block RAM Initialization problems.
FPGA_Design.zip 239 KB
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