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张雪

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[问答]

Aurora工作在0.625Gbps但不是1.25Gbps

我在sp605开发套件上使用了极光设计示例。
我正在使用SMA同轴电缆将TX通道环回到RX通道。
我的0.625Gpbs设计让通道和线路锁定得很好。
我的1.25Gbps版本没有链接。
我尝试过增加TX预加重,差分输出摆幅和RX均衡等功能无济于事。
有谁知道为什么这可能是一个问题?
我使用125Mhz PCI时钟作为参考时钟。

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I am using the example aurora design on a sp605 development kit.  I am looping back the TX channel back onto the RX channel using SMA coaxial cables.  My 0.625Gpbs design gets channel and line locked just fine.  My 1.25Gbps build does not link.  I have tried things like increasing TX pre-emphasis, diff output swing and RX equalization to no avail.  Does anyone have any idea why this may be an issue?  I am using the 125Mhz PCI clock for my reference clock.

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潘晶燕

2019-5-30 10:02:53
R,
您将需要检查信号。
为此,您需要一个非常快速的示波器(很可能是采样范围),并且可能需要一个误码率测试装置(BERT)来将发送和接收分开作为问题的根源。
对于这些非常高速的界面来说,这始终是一个挑战:当它们工作时,它们很棒,当它们不工作时,你几乎没有可见性。
我会检查发射抖动(使用合适的仪器,许多高速采样示波器都有抖动测量包)。
如果参考时钟不符合MGT的规格,则可能是问题(以低速工作,高速断开)。
你能提供一个来自已知良好工作台源的时钟吗?
在短环回,信号电平,均衡等可能不是问题。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

r,
 
You are going to need to examine the signal.  For this, you will need a really fast oscilloscope (sampling scope very likely), and perhaps a bit error rate test set (BERT) to separate the transmit, from the receive, as the source of the problem.
 
That is always the challenge with these very high speed interfaces:  when they work, they are great, when they don't, you have veirtually no visability into their workings.
 
I would check the transmit jitter (with the proper instrument, many high speed sampling scopes have jitter measurement packages).  If the reference clock is not in specification for the MGT's, this may be the problem (works at slow speed, breaks at high speed).  Can you supply a clock from a known good bench source?
 
On a short loopback, signal level, equalization, and so on is likely not the problem.
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
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曾玲娟

2019-5-30 10:08:01
你也应该熟悉CSP SIOTK的IBERT:
http://www.xilinx.com/tools/cspro.htm
http://www.xilinx.com/cn/support/documentation/boards_and_kits/ug752.pdf(SP623 IBERT入门指南)http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/chipscope_pro_sw_cores_ug029.pdf(ChipScope Pro)
12.4软件和内核用户指南)
干杯,
BT

以上来自于谷歌翻译


以下为原文

You should also likely become familiar with CSP SIOTK's IBERT:

http://www.xilinx.com/tools/cspro.htm

http://www.xilinx.com/support/documentation/boards_and_kits/ug752.pdf (SP623 IBERT Getting Started Guide)
http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/chipscope_pro_sw_cores_ug029.pdf (ChipScope Pro 12.4 Software and Cores User Guide)

 

Cheers,

bt

 
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甘晓茵

2019-5-30 10:20:56
哦,有一件事我忘了提到它与IBERT一起工作得很好。
通过IBERT,我测试了0.625,1.25和2.5 Gbps。
所以我怀疑它与物理接口有什么关系。
最有可能的是它与GTP磁贴设置有关。
无论是Aurora逻辑还是Aurora逻辑的问题。

以上来自于谷歌翻译


以下为原文

Oh one thing I forgot the mention is that it works just fine with the IBERT.  With the IBERT I have tested at 0.625, 1.25 and 2.5 Gbps.  So I doubt it has anything to do with the physical interface.  Most likely it has to do with the GTP tile setting.  Either that or a problem with the Aurora logic.
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