R,
您将需要检查信号。
为此,您需要一个非常快速的示波器(很可能是采样范围),并且可能需要一个误码率测试装置(BERT)来将发送和接收分开作为问题的根源。
对于这些非常高速的界面来说,这始终是一个挑战:当它们工作时,它们很棒,当它们不工作时,你几乎没有可见性。
我会检查发射抖动(使用合适的仪器,许多高速采样示波器都有抖动测量包)。
如果参考时钟不符合MGT的规格,则可能是问题(以低速工作,高速断开)。
你能提供一个来自已知良好工作台源的时钟吗?
在短环回,信号电平,均衡等可能不是问题。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
r,
You are going to need to examine the signal. For this, you will need a really fast oscilloscope (sampling scope very likely), and perhaps a bit error rate test set (BERT) to separate the transmit, from the receive, as the source of the problem.
That is always the challenge with these very high speed interfaces: when they work, they are great, when they don't, you have veirtually no visability into their workings.
I would check the transmit jitter (with the proper instrument, many high speed sampling scopes have jitter measurement packages). If the reference clock is not in specification for the MGT's, this may be the problem (works at slow speed, breaks at high speed). Can you supply a clock from a known good bench source?
On a short loopback, signal level, equalization, and so on is likely not the problem.
Austin Lesea
Principal Engineer
Xilinx San Jose
R,
您将需要检查信号。
为此,您需要一个非常快速的示波器(很可能是采样范围),并且可能需要一个误码率测试装置(BERT)来将发送和接收分开作为问题的根源。
对于这些非常高速的界面来说,这始终是一个挑战:当它们工作时,它们很棒,当它们不工作时,你几乎没有可见性。
我会检查发射抖动(使用合适的仪器,许多高速采样示波器都有抖动测量包)。
如果参考时钟不符合MGT的规格,则可能是问题(以低速工作,高速断开)。
你能提供一个来自已知良好工作台源的时钟吗?
在短环回,信号电平,均衡等可能不是问题。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
r,
You are going to need to examine the signal. For this, you will need a really fast oscilloscope (sampling scope very likely), and perhaps a bit error rate test set (BERT) to separate the transmit, from the receive, as the source of the problem.
That is always the challenge with these very high speed interfaces: when they work, they are great, when they don't, you have veirtually no visability into their workings.
I would check the transmit jitter (with the proper instrument, many high speed sampling scopes have jitter measurement packages). If the reference clock is not in specification for the MGT's, this may be the problem (works at slow speed, breaks at high speed). Can you supply a clock from a known good bench source?
On a short loopback, signal level, equalization, and so on is likely not the problem.
Austin Lesea
Principal Engineer
Xilinx San Jose
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