喜
我有一个设计与以下heirarchy -
顶层
.. module1
..module2
.....单词数
module3有一个名为“link”的4位输入寄存器,我需要忽略它的时序(因为这个寄存器没有动态改变)。
在我的ucf中,我尝试了以下语法,但似乎都没有。
对于以下,我总是得到错误 - ....不匹配任何设计对象(约束系统58错误)
NET“top_level / module2 / module3 / link ”
tiG;
NET“module2 / module3 / link ”TIG;
NET“module2 / module3 / link ”TNM_NET =“fp1”;
TIMESPEC“TS_fp1”=来自“fp1”TIG;
确实没有标记错误的约束是 -
INST“module2 / module3 / link ”TIG;
我的问题是 -
1)是否有任何特殊的语法来指定设计层次内部的网络上的TIG?
2)是否有任何依赖天气的内部线/ reg或模块输入/输出?
3)如果我的设计输入是edif文件,上述内容是否会工作?
4)在什么情况下我应该使用INST,在什么情况下我应该使用NET?
帮帮我!!!
以上来自于谷歌翻译
以下为原文
hi,
i have a design with the following heirarchy -
top_level
.. module1
..module2
.....module3
module3 has an 4 bit input register called "link" on which i need to ignore the timing (because this reg is not changed dynamically).
in my ucf, i've tried the following syntaxes but none seem to work. for the following, i always got the error - .... does not match any design object (constraint system 58 error)
NET "top_level/module2/module3/link" TIG;
NET "module2/module3/link" TIG;
NET "module2/module3/link" TNM_NET = "fp1";
TIMESPEC "TS_fp1" = from "fp1" TIG;
the constraint that does go through without flagging an error is -
INST "module2/module3/link" TIG;
my questions are -
1) is there any special syntax to specify a TIG on a net that is deep inside the design heirarchy?
2) is there any dependency on weather it is an internal wire/reg or module input/output?
3) if my design input is an edif file, will the above constriants till work?
4) in what case should i use INST and in what case should i use NET?
HELP!!!