Kintex 7的最高工作频率是？

嗨，
设计的Fmax取决于所使用资源的最大规格，如缓冲区，时钟模块，编码，路由等。
您可以实施设计和检查时间报告。
还运行IBIS smluations来检查SI。
另请参阅Kintex -7的数据表，了解电气规格和开关特性
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
通过相关讨论获得更多输入和链接
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
希望这可以帮助
-Vanitha
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在原帖中查看解决方案



以下为原文

Hi,
 
Fmax of design depends on max specifications of  resources used like buffers, clocking modules, how well you code, routing etc.
You can implement your deisgn and check timing reports.
Also run IBIS smluations to check the SI.
 
Also go through data sheet of Kintex -7 for electrical specifications and switching charateristics 
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
 
Go through relavant discussions for more inputs and links
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
 
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
 
 
Hope this helps
 
-Vanitha
---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
View solution in original post

嗨，
设计的Fmax取决于所使用资源的最大规格，如缓冲区，时钟模块，编码，路由等。
您可以实施设计和检查时间报告。
还运行IBIS smluations来检查SI。
另请参阅Kintex -7的数据表，了解电气规格和开关特性
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
通过相关讨论获得更多输入和链接
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
希望这可以帮助
-Vanitha
--------------------------------------------------
-------------------------------------------请在发布前进行谷歌搜索，
您可能会找到相关信息。请留下帖子 - “接受为解决方案”，如果提供的信息有用且回复，请给予赞誉



以下为原文

Hi,
 
Fmax of design depends on max specifications of  resources used like buffers, clocking modules, how well you code, routing etc.
You can implement your deisgn and check timing reports.
Also run IBIS smluations to check the SI.
 
Also go through data sheet of Kintex -7 for electrical specifications and switching charateristics 
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
 
Go through relavant discussions for more inputs and links
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
 
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
 
 
Hope this helps
 
-Vanitha
---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

是的，不是答案！
我有一个800 MHz的knitex runnig的PLL， 
但是你在那个时间里做不了多少，时间是1.2 ns，
整个芯片的适应性是几纳秒的顺序， 
所以，是的，你可以获得800 MHz的FF，但不要期望通过DSP和芯片获得数据。
作为参考，对于所有常见的空穴，-2部分的相对数将是250MHz，而没有太多问题。 
但是知道，具体的'我的未经验证的设计可以在800 MHz运行'。



以下为原文

yes and no is the answer !
 
I have the PLL in a knitex runnig at 800 MHz, 
   but you cant get much done in that time, period is 1.2 ns,
 
the propergation across the chip is of the order a few ns, 
   so yes, you can get a FF togling at 800 MHz, but don't expect to get data through a DSP and across the chip.
 
For reference, with all the usual caviates, relaistic  number for a -2 part would be 250 MHz, withotu too much problems.
   buta specific 'can my unsepcified design run at 800 MHz,' , who know.
 
 
 
      

嗨Vanitha，
在器件的DC特性中，提到了BUFG，BUFH等的一些数字。
但我有一个混乱，这意味着FPGA架构无法在上述数字之上运行，或者数据无法从这些数字之外的FPGA中取出。
再次在同一数据表中提到MMCM可以产生最大时钟或933MHz。
我不明白FPGA是否不支持这样的频率，那么MMCM为什么以及如何能够产生这样的频率时钟。



以下为原文

Hi Vanitha,
 
In the DC characteristics of the device some figures for BUFG, BUFH etc are mentioned. But I have a confusion that does it mean that FPGA fabrics can't be run above the mentioned figures or data can't be taken out of the FPGA above these figures. Again in the same datasheet it is mentioned that MMCM can produce max clock or 933MHz. I didn't understand if the FPGA does not support such frequencies, then why and how the MMCM is able to produce such a frequency clocks.