为什么更改define指令值会导致失败？

当设计从运行到运行失败时，如您所描述的那样，根本原因通常是设计中的时间问题。
这要么是缺少本应应用于设计的时序约束，未正确处理的时钟域交叉，要么是未正确处理的同步逻辑的异步输入。
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以下为原文

When designs fail from run to run with minor changes like you have described the root cause is usually a timing issue in the design.  This is either missing timing constraints that should have been applied to the design, clock domain crossings that are not correctly handled, or asynchronous inputs to synchronous logic that are not correctly handled.
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附件是我用于设计的ucf文件。
在这种情况下如何调试。
我不是这个项目的原始设计师，但我必须调试设计，因为原设计师离开了。
我该怎么调试呢？
谢谢
*论坛管理员删除了附件



以下为原文

The attachment is a ucf file I use for the design. How do I debug in this situation. I am not the original designer of this project, but I have to debug the design since the original designer left. How can I debug this? 
 
Thanks
 
*attachment removed by Forums admin

有没有办法让它稳定或使用一些约束，如KEEP或S属性，使其一致？



以下为原文

Is there any way to make it stable or use some constraint such as KEEP or S property to make it consistant? 

您无法使用KEEP和S约束来解决时序问题。
设计可能正在用于测试的部分，但是一旦你开始在多个部分上尝试这个，你就会开始看到失败。
您需要深入了解设计并找到根本原因。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

You cannot fix timing issues with KEEP and S constraints.  The design may be working on the part that you are using for testing, but once you start trying this on multiple parts you will start seeing failures.  You need to get in to the design and find the root cause.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com