请问有办法减少级联延迟吗？

嗨，
我想设计一个电路来输出16位数据的0的前导数。
我使用Spartan 6 EDK板和ISE 13.4。
对我来说，RTL视图显示来自此行的16个级联逻辑并不奇怪：
开始
din_signed
num0 to_signed（15,5）when（din_signed（15 DOWNTO 1）=“000000000000000”）否则to_signed（14,5）when（din_signed（15 DOWNTO 2）=“00000000000000”）否则to_signed（13,5）when（din_signed
（15 DOWNTO 3）=“0000000000000”）否则to_signed（12,5）当（din_signed（15 DOWNTO 4）=“000000000000”）否则to_signed（11,5）当（din_signed（15 DOWNTO 5）=“00000000000”）
否则to_signed（10,5）当（din_signed（15 DOWNTO 6）=“0000000000”）否则to_signed（9,5）当（din_signed（15 DOWNTO 7）=“000000000”）否则to_signed（8,5）当（din_signed）
（15 DOWNTO 8）=“00000000”）否则to_signed（7,5）当（din_signed（15 DOWNTO 9）=“0000000”）否则to_signed（6,5）when（din_signed（15 DOWNTO 10）=“000000”）
否则to_signed（5,5）当（din_signed（15 DOWNTO 11）=“00000”）否则to_signed（4,5）当（din_signed（15 DOWNTO 12）=“0000”）否则to_signed（3,5）当（din_signed）
（15 DOWNTO 13）=“000”）否则to_signed（2,5）当（din_signed（15 DOWNTO 14）=“00”）否则to_signed（1,5）当（din_signed（15）='0'）否则to_signed
（0,5）;
我希望项目运行得更快。
我想应该用更多的逻辑来完成，但我不知道该怎么做。
有办法到达那里吗？
附加了vhdl文件和RTL视图文件。
谢谢，
leadingz.vhd 3 KB

以上来自于谷歌翻译

以下为原文

Hi,
I want to design a circuit to output the leading the number of 0's of a 16 bit data. I use Spartan 6 EDK board with ISE 13.4. It is not surprise to me that the RTL view shows 16 cascaded logic from this line:

begin
  din_signed    <= signed(din);
  num0 <= to_signed(16, 5) when (din_signed(15 DOWNTO 0) = "0000000000000000") else
      to_signed(15, 5) when (din_signed(15 DOWNTO 1) = "000000000000000")  else
      to_signed(14, 5) when (din_signed(15 DOWNTO 2) = "00000000000000")  else
      to_signed(13, 5) when (din_signed(15 DOWNTO 3) = "0000000000000")  else
      to_signed(12, 5) when (din_signed(15 DOWNTO 4) = "000000000000")  else
      to_signed(11, 5) when (din_signed(15 DOWNTO 5) = "00000000000")  else
      to_signed(10, 5) when (din_signed(15 DOWNTO 6) = "0000000000")  else
      to_signed( 9, 5) when (din_signed(15 DOWNTO 7) = "000000000")  else
      to_signed( 8, 5) when (din_signed(15 DOWNTO 8) = "00000000")  else
      to_signed( 7, 5) when (din_signed(15 DOWNTO 9)  = "0000000")  else
      to_signed( 6, 5) when (din_signed(15 DOWNTO 10) = "000000")  else
      to_signed( 5, 5) when (din_signed(15 DOWNTO 11) = "00000")  else
      to_signed( 4, 5) when (din_signed(15 DOWNTO 12) = "0000")  else
      to_signed( 3, 5) when (din_signed(15 DOWNTO 13) = "000")  else
      to_signed( 2, 5) when (din_signed(15 DOWNTO 14) = "00")  else
      to_signed( 1, 5) when (din_signed(15)          = '0')  else
      to_signed( 0, 5);

I want the project runs faster. I guess it should be done with more logic, but I don't know how to do that. Is there a way to get there?
The vhdl file and the RTL view file are attached.

Thanks,
         leadingz.vhd ‏3 KB

杨玲

2019-3-18 13:18:54

RTL视图在确定代码运行速度方面不是很有用。
如果有什么需要查看技术视图。
但实际上，在逻辑之前和之后制作带寄存器的projet是有意义的，并通过它来运行它。
路线并查看P＆amp; R静态时序报告。
Spartan 6具有6输入LUT，实际实现的逻辑电平可能比您从RTL视图中看到的要少。
因此，在您知道当前实现是否足够快地运行之前，尝试改进逻辑是没有意义的。
- Gabor
在原帖中查看解决方案

以上来自于谷歌翻译

以下为原文

The RTL view is not very useful in determining how fast your code will run. If anything you need to look at the technology view. But really it makes sense to make a projet with registers before and after your logic, and run it through place & route and look at the post P&R static timing report. Spartan 6 has 6-input LUTs and it's likely that the actual implementation has fewer logic levels that you would think from looking at the RTL view. So it really doesn't make sense to try to improve the logic until you know whether the current implementation runs fast enough for you.
-- GaborView solution in original post

杨玲

2019-3-18 13:26:08

RTL视图在确定代码运行速度方面不是很有用。
如果有什么需要查看技术视图。
但实际上，在逻辑之前和之后制作带寄存器的projet是有意义的，并通过它来运行它。
路线并查看P＆amp; R静态时序报告。
Spartan 6具有6输入LUT，实际实现的逻辑电平可能比您从RTL视图中看到的要少。
因此，在您知道当前实现是否足够快地运行之前，尝试改进逻辑是没有意义的。
- Gabor

以上来自于谷歌翻译

以下为原文

The RTL view is not very useful in determining how fast your code will run. If anything you need to look at the technology view. But really it makes sense to make a projet with registers before and after your logic, and run it through place & route and look at the post P&R static timing report. Spartan 6 has 6-input LUTs and it's likely that the actual implementation has fewer logic levels that you would think from looking at the RTL view. So it really doesn't make sense to try to improve the logic until you know whether the current implementation runs fast enough for you.
-- Gabor

沈雨露

2019-3-18 13:33:16

非常感谢你！
你的回答对我很有帮助。
我在数据输入和输出都添加了寄存器。
然后我放置和路线。
时间报告如下：
din |
0.378（R）|
快点|
0.374（R）|
慢| clk_BUFGP |
0.000 |
dtmp |
7.429（R）|
慢|
3.968（R）|
FAST | clk_BUFGP |
0.000 |
clk |
2.860 |
|
|
|
打扰一下。
我从这些数据中得不到多少。
完整的报告如下。
你能给我一些关于我的设计有多快的解释吗？
leadingz.vhd 5 KB

以上来自于谷歌翻译

以下为原文

Thank you very much! Your answer is very helpful to me. I add registers at both data input and output. Then I place and route. The timing report has the following:

din<0> | 0.378(R)| FAST | 0.374(R)| SLOW |clk_BUFGP | 0.000|
dtmp<0> | 7.429(R)| SLOW | 3.968(R)| FAST |clk_BUFGP | 0.000|
clk | 2.860| | | |

Excuse me. I do not get much from these data. The complete report is attached below. Could you give me a little more explanation about how fast my design?

leadingz.vhd ‏5 KB

沈雨露

2019-3-18 13:45:33

对不起，我忘记在上一篇文章中添加计时reprot。
leadingz.zip 5 KB

以上来自于谷歌翻译

以下为原文

Excuse me I forget to add the timing reprot in last post.

leadingz.zip ‏5 KB

孙榕

回帖（11）

杨玲

杨玲

沈雨露

沈雨露

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