Xilinx不提供器件的原理图符号和布局贴花。
在布局贴花的情况下,这些设备是标准的JEDEC 1.0mm阵列,可以在布局工具中自动生成。
在原理图符号的情况下,每个/每个公司都有不同的样式(字体,分组,分割等),他们喜欢使用(或需要使用)来生成符号,这就是为什么不发布这些符号的原因。
还有一个特定的UltraScale PROM支持列表,可以在本Vivado 2014.1文档的附录C中找到。
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如果没有,你应该在发布之前。太多结果?
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以上来自于谷歌翻译
以下为原文
Xilinx does not provide schematic symbols for devices nor layout decals. In the case of layout decals, these devices are standard JEDEC 1.0mm arrays and can be auto generated within the layout tool. In the case of schematic symbols, everyone/every company has a different style (fonts, groupings, splits, etc) that they like to use (or are required to use) for generating symbols which is why these are not released.
There is a specific UltraScale PROM support list as well that can be found in Appendix C of this Vivado 2014.1 document.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Xilinx不提供器件的原理图符号和布局贴花。
在布局贴花的情况下,这些设备是标准的JEDEC 1.0mm阵列,可以在布局工具中自动生成。
在原理图符号的情况下,每个/每个公司都有不同的样式(字体,分组,分割等),他们喜欢使用(或需要使用)来生成符号,这就是为什么不发布这些符号的原因。
还有一个特定的UltraScale PROM支持列表,可以在本Vivado 2014.1文档的附录C中找到。
------您是否尝试在Google中输入问题?
如果没有,你应该在发布之前。太多结果?
尝试添加网站:www.xilinx.com
以上来自于谷歌翻译
以下为原文
Xilinx does not provide schematic symbols for devices nor layout decals. In the case of layout decals, these devices are standard JEDEC 1.0mm arrays and can be auto generated within the layout tool. In the case of schematic symbols, everyone/every company has a different style (fonts, groupings, splits, etc) that they like to use (or are required to use) for generating symbols which is why these are not released.
There is a specific UltraScale PROM support list as well that can be found in Appendix C of this Vivado 2014.1 document.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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