从9位1.2 GSPS DDR并行LVDS输出ADC连续读取数据的最佳方法是什么

您可以找到一个参考设计，用于实现专门针对XAPP524中描述的7系列器件的ADC器件的LVDS接口。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

You can find a reference design for implementing a LVDS interface to ADC devices that specifically targets 7 Series devices described in XAPP524.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

谢谢你回复mcgett。
我刚刚通过你建议的AN。
如果我错过任何东西，我不知道，但它似乎与我想要的有点不同。
我的ADC是每秒1.2千兆采样（比AN高很多）并使用9个LVDS数据通道（每位一个）。
这意味着从ADC到fpga的时钟频率为600 MHZ（DDR），这对我认为的I / O逻辑来说是可以接受的。
我很困惑如何处理这些数据。
我最初的计划是为每个位使用IDELAY和IDDR块，然后将数据输入FIFO。
但这似乎对FIFO来说有点太快了。
我想到的唯一解决方案是将我丢失的数据并行化。
IDDR之后我该怎么做？
使用ISERDES有更好的方法吗？
但是有一个非常愚蠢的问题，我从10个IOB中得到了一些信息。
我如何将它们用作任何IP的10位输入。
它可能很容易，但似乎我已经让自己陷入困境。
我必须始终使用寄存器吗？



以下为原文

Thank you for the reply mcgett. I just went through the AN you suggested. I don't knwo if i am missing anything but it seems a bit different from what i want. My ADC is a 1.2 Giga samples per second ( Much higher speed than the AN) and uses 9 LVDS data lanes ( one for each bit). This means the clock from the ADC to the fpga is coming at 600 MHZ (DDR) which is ok for the I/O logic i think. I am just confused what to do with this data. My initial plan was to use IDELAY and IDDR blocks for each bit and then get the data into an FIFO. but this seems to be a bit too fast for the FIFO. The only solution i think of is to parallelise my data which i am lost at. How can i do this after the IDDR?   is there a better way to do this using ISERDES?
 
One really silly question though, I have bits coming in from 10 IOBs. How do i use them as 10 bit input to any IP. it might be easy but it seems like i have gotten my self stuck. do i have to always use registers?

该应用程序支持1.2Gbps数据速率，并且更改代码以支持9位接口，而12或14是微不足道的。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

The application supports a 1.2Gbps data rate and changing the code to support a 9 bit interface vs 12 or 14 is trivial.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

亲爱的麦吉特
再次感谢您的回复。
老实说，我期待更多的帮助。
好事是我在睡了一夜好觉后想出了一些不那么聪明的问题。
但是，对我来说，实现此设置并不是一件轻而易举的事。
我很多其他的东西，但还没有fpga，因此我问。
所以我真的很感激，如果你只是能够用你想到的一般想法指出我正确的方向。
在我看来，你的意思是说我应该使用9个iserdes并将ADC LVDS输出的每个通道视为序列化数据。
这看起来是对的吗？
在那种情况下，我在它:)。
如果这是错误的，请告诉我。



以下为原文

Dear Mcgett
 
Again thank you for the reply. Honestly i was expecting a bit more help. the good thing is i have figured out some of my not so smart questions after a good night sleep. However it is not yet trivial for me to implement this setup. I am excellent with many other things but not yet fpga hence why i asked. so i would really appreciate it if you just could atleast point me in the right direction with the general idea you have in mind. in my own view, you mean to say i should use 9 iserdes and regard each lane of my ADC LVDS output as a serialised data. does this seem about right? in that case i am on it :) . Just let me know if this is wrong.